It took you all of 3 minutes to answer you must'nt have thought about your reply much
I think you are forgetting that the high gain op-amp with negative feedback lowers the effective output impedance (look where the negative feedback is coming from - it's after the 100 ohm resistors).
It's irrelevent where the opamp feedback is coming from .The transistor has to source current via it's emitter (it's the emitters resistance that the source current has to come through that is Re+RE where re is intrinsic emiter resitance(small) and RE is any external emitter resistor ) . Think of it like this,Re is small but even if your bjt turns hard on then max current it can source is now limited by RE . thus any load cap can only be charged at at time constant of RE*Cload
Ideal caps with zero ESR isn't the issue here. It's a widely understood fact that op-amps have stability issues when driving large capacitive loads.
then widely misunderstood it seems:) .
The problem isn't 'large caps' it's actually 'small caps' like ceramics with low esr's (Electrolytics with there large esr's are nearly always stable ,) the cap forms a pole you see with the output impedance Rout (in your case the 100 ohm resitor you put in the emitter) . this cap creates a pole at 1/2 pi C Rout+ESR so you see the bigger Rout or C then the lower frequency (bad) this pole goes . BUT any resistor in series with the capacitor forms a zero or 'anti pole' which cancels the first pole .This anti pole is at 1/2 pi C esr , so you see if ESR OR C is bigger this zero also moves down in frequency moving down with the pole and this is why you can put massive electrolytics with aparantly little esr on your power supply and it will be stable .Since if we increase capacitance but esr stays more or less the same the anti pole still goes down in frequency with the pole.
I couldn't disagree more. Since the circuit is designed to sit exactly midway between the two input rails, without the biasing scheme the transistors would continually be sitting right in the dead zone. This definitely has a detrimental effect on stability and output ripple of the circuit.
Did you even read anything what i typed before you answered ? .The time it takes for the opamp to turn on the complement bjt is small compared to how long a 10 uF capacitor can source current to the load for ,thus you may hardly wont even notice it .THATS WHY I suggested you do some load steps with lt spice and posted a bode lot so you could see a real plot of the loop response speed and a 10uS recovery
'you strongly disagree with that' ?
Let me ask you what you think the GBW of your is ? (with some real capcitive loads on it).but I think you dont need evidence you just to know yeh