What does this do? Pair of 74LS74 gates

[NivagSwerdna]

A board i am trying to fix has some timing that seems to not be correct and the crux of it seems to be a pair of D +ve edge flip flops.

A 6MHz clock, called S109, goes into both; it's 33% duty square wave.  The nQ of the first gate goes back to its D making it a divide by 2.

The Q output of the first goes to the D of the second and the nQ output of the second is designated S107.

A small 100pF cap has been soldered on the second gate clock input to ground.

I'm sure there is something very clever going on here but i cannot fathom it!

I assume the 100pF is meant to delay the clock on the second gate but why bother? Why have the second gate at all?

Thanks in advance

[David Hess]

The second flip-flop reclocks the output of the first flip-flop, and then the capacitor delays the second flip-flop to avoid a setup-and-hold time violation, which sort of defeats the idea of reclocking.  Maybe they needed the divided frequency, but then delayed it to meet setup-and-hold time requirements elsewhere?

Is a series resistor before the capacitor missing?

[fourfathom]

Is a series resistor before the capacitor missing?

Good question.  As shown the capacitor affects both clock inputs.  Unless there is a series resistor or a *very* long trace all it's going to do is perhaps filter some clock ringing.
But if there is a resistor, the second D-flop will see a delayed clock, which would be a bad thing here as it screws up the setup/hold time on the D input.  To be honest I can't see any valid reason for the second D-flop to be there and slowing down or delaying the clock transition is likely to cause problems.

I suspect the capacitor is there to smooth a badly-ringing clock caused by poor layout.  This is not a great solution but perhaps it works.  The overall design still makes no sense to me.

[langwadt]

The second flip-flop reclocks the output of the first flip-flop, and then the capacitor delays the second flip-flop to avoid a setup-and-hold time violation, which sort of defeats the idea of reclocking.  Maybe they needed the divided frequency, but then delayed it to meet setup-and-hold time requirements elsewhere?

Is a series resistor before the capacitor missing?

minimum hold should already be well below clk to Q and 6MHz is slow so setup should not be an issue

[NivagSwerdna]

Context is a bit hard because half of the circuit is inside a custom chip...



but i think I  have an equivalent circuit of the stage that comes out of pin 2...



Those two bits should add up to what i drew

[NivagSwerdna]

Here's another schematic... similar... but they decided to use 30pF here!

[David Hess]

Now it just looks like a signal integrity issue which they solved with a couple of small capacitors.

[fourfathom]

Now it just looks like a signal integrity issue which they solved with a couple of small capacitors.

Yeah, that was my final conclusion.  But ignore the capacitor(s) for now -- what is the point of that original hand-drawn circuit?  It's not a resynchronizer, not an edge-detector, not a pipeline delay section, nor does it establish a known output phase.  It seems entirely pointless.  Perhaps the sketch doesn't reflect the actual circuit?  I really can't tell from the follow-on posted schematics.

[NivagSwerdna]

The point of the hand-drawn was so show the two parts together since on the official schematics they are obscured by the fact there is a custom chip.



The 082 custom is clocked by 109 via its pin 13.   G10 here is also clocked by 109.   The 082 custom generates pin 2 which is 109 divided by 2; clocked by 109.

G10 obviously inverts it but the question was about which version it inverts; the one on the +ve edge of 109 (74LS74 is positive edge triggered) or delayed?

Perhaps it was an attempt to synchronise 107 to the 109 clock domain (and invert the signal) without making assumptions about the internal workings of the custom?

(As we now know there is a variant with 30pF and another with 100pF, but otherwise identical).

[NivagSwerdna]

FYI

I asked google AI...

Because the first flip-flop is actually hidden inside or simulated by a custom chip (the "082 custom"), the physical implementation shifts from a textbook design to a real-world hack to overcome manufacturing variations.

The Real Intent:

Fixing a Custom Chip's SkewIn the actual equipment, the custom chip generates a "divide-by-2" output (Pin 2) clocked by the master S109 clock. The second 74LS74 is trying to sample that pin.However, because the signal propagates through the internal logic of a custom silicon die, the output on Pin 2 is delayed relative to the external clock line. This creates a tight race condition between the arriving data and the clock edge at the second gate.

What the 100pF/30pF Capacitor is DoingThe small capacitor (whether 100pF on this board or 30pF on a variant) was not added to change the fundamental logic phase, but as a factory "band-aid" for signal integrity or timing alignment:

Option A (Slow Edge Filter):

As mentioned in the forum thread, the capacitor might just be there to suppress high-frequency clock ringing or glitches caused by poor board layout. In this case, the second gate successfully samples the old state, meaning nQ (S107) remains identical to Q₁.

Option B (Deliberate Hold-Time Fix):

If there is trace resistance or the clock driver is weak, the capacitor slightly nudges the clock arrival time back. It ensures the second flip-flop holds off just long enough for the custom chip's delayed output to stabilize before it samples.

So I'm still none the wiser... it either delays or is does not.

[UnijunctionTransistor]

If I had to put money on the table, my bet would be: The “factory bandaid” to correct a situation caused by component and/or manufacturing tolerances.

[Bud]

The capacitor aside, there are S and R signals on the first flip flop that we do not know where they are connected to. They maybe asynchronous to the clock and change the flip flop output arbitrarily, in which case the second flip flop helps hold the output by latching it until the next clock cycle.

[NivagSwerdna]

The capacitor aside, there are S and R signals on the first flip flop that we do not know where they are connected to.

On the schematic.  nS is pulled up to VCC.   nR on the first is connected to nRESET which is LOW initially during power up and then permanently HI.