Op-Amp driven PMOS oscillating for certain VDS values

[Peeps]

I've modified a power supply from an old server to give it voltage and current control from 1 to 14V up to 36A limit. The 1V minimum is due to smps's not being very happy below that. Therefore part of the design was to have a 1V drop before the output because being able to go to 0V is very useful for what I need.

I designed the circuit below to provide me with the 1V drop. It subtracts V_drop from V_supply and the output is taken across RL.

At first I had major stability problems, but after reading up on op-amp compensation methods I found that C2 in conjunction with a gain >> 1 for U1 made the simulation stable across all my loads and for a V_supply from 1 to 14V.

Now the real circuit doesn't work nearly as good. For V_supply from 1V to 4V, U1 oscillates badly, but is perfectly stable past that range. The oscillation frequency seems to be ~625Hz or so, as best as I can tell by reading my analog scope's divisions.

Despite the oscillation, the output voltage is correct, but I know it shouldn't be doing this and I'm stumped as to why. My circuit is layed out on strip board, which is probably the cause of some problems, but I still don't understand what's happening.





Edit: Scope is set to 5V/div and 2ms/div

[Peeps]

I've been doing some reading in the meantime and it looks like what I have here is just an LDO regulator. The PMOS allows VDS to go very low but its inherently unstable due to well, a lot of factors.

I found some great notes on it though, mainly https://www.ece.uic.edu/~vahe/spring2012/ece396/linreg.pdf and I'll be working on a compensation scheme after I get the bode plot of my circuit.

[David Hess]

The lead compensation with C2 is a good start but you need to add frequency compensation between the output of the operational amplifier and its inverting input.

The common source output transistor has variable gain depending on the load which makes frequency compensation more difficult.

The LM358 will have some trouble driving the input capacitance of the MOSFET.  This is not fatal but it will limit performance.

It would help to know the vertical and horizontal settings on your oscilloscope; they are not marked anywhere.

[Peeps]

Thank you for the input. My scope settings in the pic are 5V/div and 2ms/div.

And yeah this MOSFET has a fairly high input capacitance. Around 9nF typical...I'll see what I can do about using a different op amp or different FET but I'll work on the compensation scheme in the meantime.

[David Hess]

And yeah this MOSFET has a fairly high input capacitance. Around 9pF typical...I'll see what I can do about using a different op amp or different FET but I'll work on the compensation scheme in the meantime.

9pF?  If I understand what you are doing, it is more like 900pF.

[Peeps]

And yeah this MOSFET has a fairly high input capacitance. Around 9pF typical...I'll see what I can do about using a different op amp or different FET but I'll work on the compensation scheme in the meantime.

9pF?  If I understand what you are doing, it is more like 900pF.

Sorry, yes. 9000pF so 9nF. That's what the datasheet says.

I added 0.2ohms resistance in series with the output capacitor as it seems a minimum ESR is required to stabilize a circuit like this. It didn't change much. The circuit simulation is stable with only 0.005 ohms ESR on the output cap, and unstable with 0 ESR and the compensation capacitor removed.

My stability margin with that additional ESR is calculated to be almost 90 degrees too which should be waay more than enough to be stable. But clearly the real circuit has something more going on than the simulation is accounting for.

[Peeps]

I feel pretty dumb. I spent a long time trying to make this work because I was convinced my power supply wasn't happy below 1V. It turns out it goes right to 0V just fine so I don't need this circuit here... 

But what I did find out is that adding about 2 ohms ESR made it very stable down to around 1.5V across the mosfet. Too much ESR for this application though.

[TheUnnamedNewbie]

Yeah, LDO's can be really hard. The key is that unlike with a "regular" linear regulator, where the NPN or NMOS device acts as a kind of follower, your PMOS is going to give you extra gain - but the gain depends on the load. This makes the stability analysis very tricky as the loop gain and poles and zeros all move around depending on the load current and such.