Why does my zero offset op-amp have offset?

[jrmymllr]

I'm designing a circuit that contains a current sink, simple stuff. Four MOSFETS sharing the load, each controlled by an op-amp, so each FET is passing the same current. The op-amp offset varies from 0.6mV to at least 4mV depending on the voltage I feed into the sink. The response is not even linear. As I increase the voltage into the sink it makes the offset worse, then begins improving. The FETs are logic level so they are doing the job with around 2 volts into each gate.

This is the first I've used these chopper op-amps so I suspect it has something to do with that feature. I breadboarded one of these op-amps with a very simple test circuit and couldn't get good offset performance either. I've found some information out there about this, but nothing very helpful. I'm surprised there isn't more about this because I've used standard op-amps before and never had this problem!

By the way there is a MLCC filter cap across the device on the PCB that isn't shown in the schematic piece I've included. What is going on with this?

[MariuszD]

Have you checked if the circuit is not oscillating? Often, when the circuit oscillates, the measurements on the DC voltmeter are different from the expected values.
Between resistor R18 and pin 9, there should be a resistor.

[jrmymllr]

Have you checked if the circuit is not oscillating? Often, when the circuit oscillates, the measurements on the DC voltmeter are different from the expected values.
Between resistor R18 and pin 9, there should be a resistor.

I have not but that's a possibility. The current draw shown on my power supply (for the load) is fluctuating some.

Shoot, you're right. The C12/R6 compensation network isn't going to do much without another resistor.

[Benta]

Please redraw your schematic and use appropriate symbols (eg, opamps). A drawing of a DIP-14 package requires two levels of abstraction from viewers.
Make it easy to answer your questions.
Just a hint.

[sourcecharge]

Looking at the datasheet, your input offset voltage is 1uV, your input bias current is 300pA, and your input offset current is 600pA.

"The op-amp offset varies from 0.6mV to at least 4mV depending on the voltage I feed into the sink. "

Looking at your schematic, is seems as if the input bias current, and input offset current is dominating your offset voltage output due to a high impedance.

Checking the datasheet, it does not specify the input inpedance, but more than likely its high.

My segestion is to first add a 50 ohm to 300 ohm input resistance for each opamp so that each input is isolated to prevent oscliation, and second, use a 50 ohm resistance to ground from your input voltage reference.

This will limit your input bias current and input offset current by clamping the input impedance to <350 ohms.

350ohms x 600pA = <180nV

Next, why are you using a 1nF cap in series with the 1K ohm resistance when all you are doing is using them as buffers?

I would take those out and just connect the output to the - input as the datasheet states that these chips are:

"Applications Information
ADC Buffer Amplifier
The MAX44241/MAX44243/MAX44246 have low input offset voltage, low noise, and fast settling time that make these amplifiers ideal for ADC buffers.
Weight scales are one application that often requires a low-noise, high-voltage amplifier in front of an ADC.
The Typical Operating Circuit details an example of a load cell and amplifier driven from the same ±10V supplies, along with the MAX11211 18-bit delta sigma ADC.
Load cells produce a very small voltage change at their outputs; therefore driving the excitation source with a higher voltage produces a wider dynamic range that can be measured at the ADC inputs.
The MAX11211 ADC operates from a single 2.7V to 3.6V analog supply, offers 18-bit noise-free resolution and 0.86mW power dissipation.
The MAX11211 also offers > 100dB rejection at 50Hz and 60Hz.
This ADC is part of a family of 16-, 18-, 20-, and 24-bit delta sigma ADCs with high precision and < 1mW power dissipation.
The low input offset voltage and low noise of MAX44241/MAX44243/MAX44246 allow a gain circuit to precede the MAX11211 without losing any dynamic range at the ADC.
See the Typical Operating Circuit."

This does not specify that a resistance is needed for use as a buffer, which they normally tell you what resistance to use if it is not a unity gain stable opamp.

If you are using it for compensation, I would put the capacitance in parallel with the resistance, not in series, but normally, buffers don't need compensation.

Lastly, do you really need 4 op amps to drive these mosfets?

Data sheet says 30mA mA min. so assuming 30Vdd, and a max output of 30V, simply increase the 1k to 10kohms on each mosfet.

Drive all four with one opamp, and use the 3 others for something else.

I hope that helps.

[MariuszD]

Looking at your schematic, is seems as if the input bias current, and input offset current is dominating your offset voltage output due to a high impedance.
...
 use a 50 ohm resistance to ground from your input voltage reference.
...
Next, why are you using a 1nF cap in series with the 1K ohm resistance when all you are doing is using them as buffers?
...
If you are using it for compensation, I would put the capacitance in parallel with the resistance, not in series...
...
Drive all four with one opamp, and use the 3 others for something else.

Don't use LLM. How many times do people need to be told that LLMs cannot analyze circuits, they were not created for that.
This deserves the award bullshit of the month.

[sourcecharge]

Looking at your schematic, is seems as if the input bias current, and input offset current is dominating your offset voltage output due to a high impedance.
...
 use a 50 ohm resistance to ground from your input voltage reference.
...
Next, why are you using a 1nF cap in series with the 1K ohm resistance when all you are doing is using them as buffers?
...
If you are using it for compensation, I would put the capacitance in parallel with the resistance, not in series...
...
Drive all four with one opamp, and use the 3 others for something else.

Don't use LLM. How many times do people need to be told that LLMs cannot analyze circuits, they were not created for that.
This deserves the award bullshit of the month.

um, no, I didn't use anything other than what I know.

If you feel as if you know better, please by all means, tell me where I'm wrong.

And yes, he has a 0.1 ohm shunt after the 1kohm/1nF pair, but that is wired incorrectly, I believe.

I didn't see that before, but this is really the first time anyone has told me i sound like a LLM.

 

And btw, let me add that before grok went full on datamining, requiring a login, I found that it was more helpful than this place, with instant feedback.

It could absolutely analyze schematics, and pictures.

It wont be long before judgement day, and we all know it's coming.

[David Hess]

It is oscillating because the feedback network to prevent it is operating into the low impedance of the current shunts, so has practically no effect.

Add series resistors between the current shunts and inverting inputs.

[MariuszD]

um, no, I didn't use anything other than what I know.
If you feel as if you know better, please by all means, tell me where I'm wrong.

A human cannot make so many mistakes at once while writing with full confidence that they are right. That's why I know it's not a human. A human can't be that stupid.

Looking at your schematic, is seems as if the input bias current, and input offset current is dominating your offset voltage output due to a high impedance.

You wrote that the cause is high impedance, but there isn't any on the schematic; all are low or very low.

use a 50 ohm resistance to ground from your input voltage reference.

50 Ohms is a very low resistance; most reference voltage sources and operational amplifiers do not have the current output capability to handle 50 Ohms.

Next, why are you using a 1nF cap in series with the 1K ohm resistance when all you are doing is using them as buffers?

Author is building a current sink, he wrote it clearly, type it into Google and you'll get similar schematics in response. Where did you get the idea that this is a buffer?

If you are using it for compensation, I would put the capacitance in parallel with the resistance, not in series...

A parallel connection of the resistor would reduce the gain and accuracy. You won't find such solutions in books or on the internet.

Drive all four with one opamp, and use the 3 others for something else.

In current sources, it would cause an uneven distribution of currents and damage to the MOSFETs.

[Terry Bites]

Why hint that schematics on the forum are often a shocking mess, butts need kicking!

I often get weary and very despondent trying to unravel the spaghetti heaps on this forum.
What has happened to the honourable art of drawing schematics?

How people are able to make a hopeless mess with CAD tools with good schematic capture is beyond me.
There are a plethora of great packages, many free ones. So, no excuses guys.

Bad schematics channel a heady mix of fast food stained carpets, crusty sheets and a neglected toilet straight out of the page!

[MariuszD]

How people are able to make a hopeless mess with CAD tools with good schematic capture is beyond me.
There are a plethora of great packages, many free ones. So, no excuses guys.

The answer is simple: learning how to draw schematics has been replaced by learning how to use software. 
If the diagram had been properly drawn, the author would have noticed the lack of resistors themself.

[sourcecharge]

um, no, I didn't use anything other than what I know.
If you feel as if you know better, please by all means, tell me where I'm wrong.

1) A human cannot make so many mistakes at once while writing with full confidence that they are right. That's why I know it's not a human. A human can't be that stupid.

Looking at your schematic, is seems as if the input bias current, and input offset current is dominating your offset voltage output due to a high impedance.

2) You wrote that the cause is high impedance, but there isn't any on the schematic; all are low or very low.

use a 50 ohm resistance to ground from your input voltage reference.

3) 50 Ohms is a very low resistance; most reference voltage sources and operational amplifiers do not have the current output capability to handle 50 Ohms.

Next, why are you using a 1nF cap in series with the 1K ohm resistance when all you are doing is using them as buffers?

4) Author is building a current sink, he wrote it clearly, type it into Google and you'll get similar schematics in response. Where did you get the idea that this is a buffer?

If you are using it for compensation, I would put the capacitance in parallel with the resistance, not in series...

5) A parallel connection of the resistor would reduce the gain and accuracy. You won't find such solutions in books or on the internet.

Drive all four with one opamp, and use the 3 others for something else.

6) In current sources, it would cause an uneven distribution of currents and damage to the MOSFETs.

1. The same can be said about you, so stop.

I have tried to be respectful of you but my patience has run out.

As I told you before, Im not an LLM, and Im not using an LLM.

You disrepected me because you don't understand what I'm talking about regarding high impedance.

One more time, and I'm reporting you.

2. The + inputs of the opamps have high inpedance. 

Since they are paralleled, they are feeding current back into each other, and no, there is not a resistor on the schematic. 

You would have to know the properties of opamps to understand this.

I tried to even explain this by stating that there was no Input impedance listed on the datasheet, but even the shittiest opamps usually have high impedance on their + inputs. 

3. 50 ohms would be a standard. 

Depending on how much the Voltage Reference can handle, simply adjusting this resistance so that the current is not too high should be fine. 

Or, if only one opamp is used, then the resistor to ground is not needed.

4. The question was about the offset voltage of the opamps not the current sink.

As I was finishing up answering the reason why he is getting high offset, I quickly glanced at the schematic, but I did not notice the output was going to a shunt.   

The schematic looked to me like the opamps were feeding to a 220 which had a 1k ohm resistor to ground after it. 

"And yes, he has a 0.1 ohm shunt after the 1kohm/1nF pair, but that is wired incorrectly, I believe.
I didn't see that before,"

I've never used a "current sink" like this before, so I've learned something new today. 

Most of the time when I parallel mosfets like the IRF530, I just connected all inputs in parallel. 

Seems to work just fine with much less how do you do and more to the point. 

5. Ok, if what you are saying is true but you are blocking the DC with a series conection so unless it's always an AC signal, the parallel connection increases usablity. 

I'm not sure how using a compansation cap is going to increase accuracy due to value tolerance of caps being low.

6. The way I saw this before is that there are mosfets in parallel, being driven by a 1x amplification. 

I see now that the amplification is high. 

I'm not sure if this is a mistake, but like said before, I've not used "current sinks" like this before.

[mawyatt]

This is just a simple NMOS current sink with 4 in parallel. The "gain" is 10A/V (0.1Ω Sense Resistor) for each section.

It's a little difficult to follow because the way the schematic is draw and using the rectangle for the 4 op-amps in the package as mentioned by others.

The basic problem we see is that the compensation network for each sink and op-amp (1 of 4) won't work properly because it's working into the sense resistor at 0.1Ω as "seen" from the op-amp inverting input. This needs a series R ~10kΩ from the sense resistor back to the op-amp inverting input to allow a reasonable impedance for the compensation network to work into.

As mentioned, as shown the circuit is likely oscillating and reliable measurements are questionable. A simple Bode analysis or measurement should also show this.

Edit: A simple way to understand without getting into Bode Analysis, feedback systems, and such, is the series R and C compensation bypasses the NMOS device at higher frequencies. Since the NMOS gate is bypassed the system experiences less gain at higher frequencies and less prone to oscillation. The NMOS device adds considerable delay between the gate and the source current which is sensed by the sense resistor. Uncompensated this delay causes the phase to increase and approaches 180 degrees as frequency increases, this added to the inverting op-amp phase (180 degrees) begins to approach 360 degrees or positive feedback and the system becomes unstable.

With the series R C compensation the feedback phase is kept below 180 degrees until around the entire loop the overall gain is less than unity and oscillations can't be sustained. The amount of feedback phase away from 180 degrees at unity loop gain (0dB) is called Phase Margin and the amount of gain below unity (usually in dB) when the feedback phase is 180 degrees (overall loop phase 360 degrees) is called Gain Margin. This all of course is for linear systems.

As a side note, one of things that brought a smile after retiring was purchasing our 1st DSO (we had DSOs before but they were company owned). When we discovered the built-in Bode capability this was a total surprise to have this ability built-in and this good (previously this was Instrument Network Analysis territory)!! The problem being discussed is an ideal use of such and one can glean significant hands on knowledge. Learning Bode Analysis with linear systems is a fascinating area of study and having hands on capability is icing-on-the-cake IMO. Please don't discount the value of this valuable tool for investigating areas like this discussion

Anyway, hope this helps.

Best

[dietert1]

Don't know whether it has been mentioned before: Even "rail-to-rail input" opamps have their limits. The circuit may work close to the Gnd rail, as shown in the schematic, but not as intended. If you want precision, better provide some negative supply for the opamps.

Regards, Dieter

[mawyatt]

Don't know whether it has been mentioned before: Even "rail-to-rail input" opamps have their limits. The circuit may work close the Gnd rail, as shown in the schematic, but not as intended. If you want precision, better provide some negative supply for the opamps.

Regards, Dieter

Not to mention some of the older op-amps would have the output flip-phase when the input Common Mode was exceeded!! Imagine how closed loop control loops responded to that

Best

[Benta]

Why hint that schematics on the forum are often a shocking mess, butts need kicking!

I often get weary and very despondent trying to unravel the spaghetti heaps on this forum.
What has happened to the honourable art of drawing schematics?

Terry, don't be hard on beginners. It takes time to learn, give 'em a hand in a nice way.

The bigger problem with bad schematics are websites that promote the "Lots of Little Boxes with 500+ Labels" style of non-schematics.
Sadly, those are the inspiration for beginners, it seems.

[Terry Bites]

Error checking in CAD can't spot poor design.

Part of my degree was a technical drawing module for mechanics and electronics.
You know, with a ruler, paper, pencil and ink and stencils for the rich kids. It set me up for life.
In the world of work, as schematics got passed from irritable engineers to grouchy draftsmen to suicidal pcb guys and back, a lot of errors and bad ideas got spotted and fixed.

[moffy]

Error checking in CAD can't spot poor design.

Part of my degree was a technical drawing module for mechanics and electronics.
You know, with a ruler, paper, pencil and ink and stencils for the rich kids. It set me up for life.
In the world of work, as schematics got passed from irritable engineers to grouchy draftsmen to suicidal pcb guys and back, a lot of errors and bad ideas got spotted and fixed.

Sadly, Terry is more right than wrong, technical drawing of schematics is lacking and a dying art, and just like a good pcb layout it takes time and thought to make a good drawing. A good schematic is like good  prose clear and easy to understand.

[jrmymllr]

Why hint that schematics on the forum are often a shocking mess, butts need kicking!

I often get weary and very despondent trying to unravel the spaghetti heaps on this forum.
What has happened to the honourable art of drawing schematics?

How people are able to make a hopeless mess with CAD tools with good schematic capture is beyond me.
There are a plethora of great packages, many free ones. So, no excuses guys.

Bad schematics channel a heady mix of fast food stained carpets, crusty sheets and a neglected toilet straight out of the page!

Ok, I get it, my schematic is hard to read. I'm hardly a beginner but the original purpose of this schematic was not to post online, but to generate a netlist for PCB layout and to have a record of the circuit for my own use. Making it pretty and easy to read was not a priority at that time.

It was too easy to take a screen capture of that part to post here because I had unexpected problems, which other forum members pointed out and made me realize I made a dumb mistake in the circuit.

I have to make nice schematics for my employer, but I get paid for the time so I don't mind

[richardax]

As others have said, you have oscillation. Move R6 to between shunt and op-, leave C12 between op- and out. Not sure what application this is for, you may want to decrease C12 if you need it fast. You can also add a resistor in series with C12. And may want to reduce or remove the gate resistor. All depends on application and requirement.

[jrmymllr]

As others have said, you have oscillation. Move R6 to between shunt and op-, leave C12 between op- and out. Not sure what application this is for, you may want to decrease C12 if you need it fast. You can also add a resistor in series with C12. And may want to reduce or remove the gate resistor. All depends on application and requirement.

Oscillation is confirmed, several 10s of kHz which varies with load and voltage. The issue with the compensation network is now fixed with a PCB bodge and will get fixed on another layout rev.

I also ditched the auto zero op-amp because of non-stop problems with that. I'm sure they're great and all, but it was a nice-to-have and a normal op-amp is far more predictable and stable in this application. I understand the internal switching can cause problems if not dealt with and I'm likely better off avoiding all that for now.

[jrmymllr]

Why hint that schematics on the forum are often a shocking mess, butts need kicking!

I often get weary and very despondent trying to unravel the spaghetti heaps on this forum.
What has happened to the honourable art of drawing schematics?

Terry, don't be hard on beginners. It takes time to learn, give 'em a hand in a nice way.

The bigger problem with bad schematics are websites that promote the "Lots of Little Boxes with 500+ Labels" style of non-schematics.
Sadly, those are the inspiration for beginners, it seems.

I'll be honest and say I'm nowhere near a beginner. I'm a degreed EE with many years experience, but what everyone is seeing here is output from my hobbyist side. The schematic was a way to produce a PCB and have the schematic for future reference, originally intended for my eyes only. For that, it did the job. This all takes time, most was spent on the PCB layout which I'd say is far more important. Making the schematic pretty and nice takes more time, which I have too little of because of a wife and kids and house and yard work, not to mention a full time job that competes for my time.

It was easy to grab a screenshot of that piece of the schematic when I encountered unexpected problems and many here were nice to help. In hindsight the design errors I made were dumb and I should have known better. However I'm finding no matter how hard I tried, I have discovered other stupid errors and this will not be a single revision PCB!

[Benta]

I have to disagree. Making a nice schematic does not take a lot more time that making a crap one, and as of now you've wasted your own, and worse, OUR time with it, apparently because you couldn't even decode it yourself.

[jrmymllr]

I have to disagree. Making a nice schematic does not take a lot more time that making a crap one, and as of now you've wasted your own, and worse, OUR time with it, apparently because you couldn't even decode it yourself.

Sheesh I never expected this level of criticism over a partial schematic. And why do you think I was unable to decode it myself? I drew it, I know the circuit. But I made a mistake because I was overly fixated on other parts of it. Have you never done that?

EDIT: I get the SCH is not up to some expectations. But then to accuse me of not being able to decode it myself! TOUGH CROWD!

[Benta]

TOUGH CROWD!

Depends. My experience with this site is that it's friendly and tries to help both beginners and experienced people. Remember, this is on our free time.

But now that you've outed yourself as an experienced EE, gloves are off.
Posting a "schematic" like you did is less than respectful.
Mindset seems to be: " let the other idiots work it out for me, I'm too lazy to make it readable."

Not the best approach IMO.

So yes, in this case I'm "tough".

Over and out from my side.