A power transistor would need to be used
Thanks yes, we are indeed using a SOT223 BJT, gap padded to the heatsink.
Thanks Zero999, really great circuit!
(looks like it latches off, ill have another check later)
Yes, it latches off, due to the action of D1. It can be reset by cycling the power or briefly connecting U1's output to 0V.
Here's a circuit which implements the ideas I mentioned in my previous post.
D3 & D4 limits the peak current to around 200mA, by clamping the voltage on Q1's base, to 1.4V, below +V, thus limiting the voltage across R5 to 0.6V.
The tripping current is still 80mA, but there are time delays, as explained below.
C1 delays the off time. It's about 500ms in this case. It depends on the values of R1 to R4 and how much current is being drawn. If it's lightly loaded, the delay will be longer, than loaded up to the maximum.
C2 limits the off time, about 1.5s, thus converting U1 into a monostable, rather than a bistable latch. Again the current affects this delay. D2 allows C2 do discharge, when U1's output goes low.
C3 ensures the circuit oscillates when the output is continuously subjected to an overload, by introducing positive AC feedback. It might not be required in real life. I just found, it acted as a linear regulator when simulated, with the load resistance continuously set to 50R.
Note the off time is much shorter, when the overload is prolonged and there isn't chance for the C1 to discharge.
The circuit is simulated by first applying a 500R load, drawing around 40mA. After 4s, the load resistance is reduced to 50R for a further second, which would try to draw 400mA, but it's limited to 200mA, until the delay times out and it switches off. At 5s the load resistance is increased to 500R again, but no current flows, until it auto-resets. At 10s the load is reduced to 50s again and is left there to demonstrate the hiccup mode and short 200mA pulses pass at a low duty cycle.
