The LT1006 is precision single supply, effectively a precision 324/358. The LT1028 is fast precision low noise. The LT1022 is fast low input bias current but since it is inverting, its common mode rejection is not important; it is suppressing common mode operation of the LT1028. The LT1010 could be replaced by a diamond buffer.
I never understood why the LT1022 was used instead of another LT1028, but it was the fastest JFET part LT made at the time. The newer and faster LT1122 should work as an improved replacement.
It has been so long that I have looked at it, 20+ years, that I forgot that, and forgot that I had a plan to get around it by making the JFET gain control floating. But you are correct, that is obviously why Jim Williams did it that way.
Incidentally, I was looking at the LT1122 datasheet and they do recommend it as an improved replacement for the LT1022 in this application.
And I am sure someone else mentioned it but I will again, figures 47 and 48 are swapped in the application note.
I have not figured out how to make the JFET VGC floating, but I would be more than happy to achieve the 0.0018% THD Williams did with ground-referenced VGC.
I have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837
I have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837
LT1028 - NE5532 or LM837
LT1022 - TL072
LT1006 - TL072 but with negative supply
LT1010 - Discrete diamond buffer
You can still buy CdS photocells so get one and make the linear optocoupler with some black heat shrink tubing and an LED or bulb.
Or for the JFET version of Jim William's circuit:
LT1115 - NE5532 or LM837
LT1055 - TL072
Now I have to wonder why he replaced the LT1115 with the LT1028. Were two different projects from different times combined into one application note?
And I made a typo - I meant LM6171/LM6172 (not LM4671/LM4672)
Discrete diamond buffer? Won't an LM6171 do?
It has 18 ppm distortions instead of only 3 ppm.
Why is that considered a refinement?
With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.
....
With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.
I have seen that THD is something like exponentially proportional to oscillator RMS. What if I use the lowest-noise opamp I have - NJM2114L
If we'll look at your oscillator spectrum at your post « #111 on: April 21, 2021, 09:43:00 pm », then we see there that noise is not your problem. The main THD contributor is a non-linearity.
One can reduce the voltage at the JFET with the parallel resistor. The downside is that this also reduces the adjustment range, so one needs the resitors / capacitors to set the frequency to be better tuned.
One the other side on could add adjustment range by switching in some resistors digitally, e.g. with relays or low R MOSFETs. This would add digital coarse trim, so one can get away with less analog trim via the JFET. With 2 digitally switched resistor one could reduce the needed range from the up to 4 times.
Having the resistor in parallel to the FET absorbes some of the variable part. So it maybe better to use more like a lower resistance fet (e.g. 2N4393 or the like).
It is not just the nonlinearity from the JFET, the amplifier can also contribute to distortion.
The variations in the required feedback setting with frequency are not so much the GBW of the OP. A main part are just tolerances of the capacitors / resistors to set the frequency. There is nothing magic about a gain of 3. Depending on the R and C in the frequency setting network, the required gain can be from some 2.7 to 3.3. So one can trim the resistors to get a more uniform gain.
The relatively low value resistor in parallel to the JFET limits the adjustment range and may help to get a more uniform response for the amplitude control loop. However it requires a higher voltage at the FET to get the same trim range.
A lower resistance FET and less effect of the parallel resistance could help to operate the FET with less voltage across. The difficulty is that the control side gets less linear and thus the stability of the amplitude control loop gets slightly more difficult. One may have to adjust R4 slightly different and possibly limit the voltlage at the gate, not to turn the FET off too much.
How much adjustment range are we looking at here?
My understanding of JFETs is, they're most linear for |Vds| < Vgs - Vp. So, for a given peak amplitude |Vds|, higher Vp is desirable, and Rds should be varied from Rds(on) to maybe a few times higher, before the above limit is reached. The important thing being, Rds is not, in general, adjustable all the way from Rds(on) to infinity, in a linear manner, for any given |Vds|.
(I don't think that's modified by the linearization (resistors from D to G to bias), but I would be interested to see evidence otherwise.)
We shouldn't need to hand-wave and empirically study this system; we need only know the range of resistance required, and this can be found by measuring the bias / control voltage while varying only a series resistor in the path (and not trying to reduce Vds or adjust resistance range with a series-shunt resistor divider before it). By plotting Rs vs. operating conditions/settings (frequency and temperature I suppose?) we can determine the minimum and maximum required values. Further, we can tweak ranges as needed to tighten up this spread. Finally, we can design a JFET circuit to deliver the required adjustment range, and that should simply be it. With the JFET operating in, whatever its most linear range is (if not Vgs ~ 0 then wherever -- this can also be measured independently by setting up a voltage divider with it).
I suspect series/shunt resistors are just a hack, as if you don't need that adjustable range in the first place, why use that JFET at all, or why not change all resistor values to simplify the circuit? (Given that the feedback resistance can't drop too far due to op-amp capacity, nor rise too much due to capacitance and leakage.)
I haven't been following this thread in great detail so I may've missed this, but I don't recall this having been performed, or proposed, yet.
Tim