Ah, that's what you meant with "how [you] want to run the gates". So, inverter, class D amp, something like that.
Depletion is no different from enhancement besides Vgs(th) being offset below rather than above zero. Put a coin cell in series with the gate and you have a fake depletion MOS, it's that trivial. Well, they can make 'em without having to use an external source of charge, which is rather convenient, so there you go.
BJT, I suppose if you're not familiar with their behavior in general (Ic ~ Ib*hFE ~ exp(Vbe)) it won't be obvious, but on the upside there's only one free variable in the circuit (the bias resistor) and component ratings have to be chosen for operating area regardless so you aren't going to hit a problem there. Be mindful of SOA, which is necessary for any type, both BJT and MOS exhibit 2nd breakdown.
Since BJT draws base current, that, with maximum load current, sets minimum resistor value at minimum Vin. Zener and resistor dissipation are then set by Vin(max). Vout is just whatever's left.
MOSFET doesn't draw gate current so just bias the zener within tolerance and go. There are families of zeners specified for rated voltage at low currents (and maybe have lower noise in that condition? I'm not sure), which may be helpful here. Vout is somewhat above Vz (or below for enh. mode), and by how much, depends on Iout. See the transfer curve (Id vs. Vgs). Of course with enh. mode, this affects dropout, but depl.'s dropout is limited by Rds(on) only.
SEPIC is no different from buck or boost, you just need a dual winding inductor, an extra bypass cap (across the inductor), and output rectifier(s) for multiple outputs (with more taps on the inductors, or multiple windings wired appropriately e.g. Coilcraft Hexa-Path). Getting all of those under a buck is probably a challenge from western sources, but China, should be able to find things easily enough.
Tim