Method for Paralleling large numbers of SMPS?

[Faringdon]

Here attached is a way to do multiple SMPS in parallel.  There is a single error amplifier. The control signal voltage is converted to a PWM, then isolated via a digital isolator, then transported to each controller. This method has absolutely no limit to the number of modules that could be paralleled, because of the single error amp and the control voltage isolation.........the problem when using huge numbers of paralleled modules, is that the ground potential is not the same at each SMPS, so this gives problems....but the attached totally solves this problem. (because for this method, it doesnt matter if ground potential is different at each module).
This method also regulates the output voltage to one value, and doesnt need for example, the vout to get decreased as output current increases...unlike another well known "multiple SMPS in parallel" regime called “active droop”.

Do you agree that the attached is the "de facto" method for paralleling huge numbers of SMPS's?

(LTspice and pdf schem attached)

[rs20]

1. I wonder how PC motherboards (which have many so-called "phases" -- basically separate SMPSs running out of phase with each other to share the load and mostly cancel out the ripple) are wired up?

2. It took me a good minute or two to parse that schematic PDF... I'd strongly suggest moving the error amplifier section to the left-hand side of the schematic. That way it isn't just randomly tucked in to one of the SMPS's, and stands clearly on its own as the one single thing that is controlling all 3 SMPSs (obviously the "control should flow from left to right on a schematic" rule gets a bit subjective when there's a control loop, but I'd argue if the control gets split among three separate systems, that one thing driving everything should come first)

[ogden]

Do you agree that the attached is the "de facto" method for paralleling huge numbers of SMPS's?

No. Your approach do not account for component (in)tolerances. Run worst case simulation with one channel having maximum output (due to component value errors), another minimum output. Hopefully even by reading what I just said, you will understand flaw of your design. Instead of isolators use simple solution known for more than 100 years, star ground.

[Kleinstein]

The usual way is to run the SMPS part in sync with the same clock and just phase shifted. There are ready made chips for multiple phases.
There is extra savings in the filter caps, as the ripple current is also phase shifted and will to a large part cancel out. So one can save on the capacitors.
Running muplitple SMPs in parallel with deparate clocks is calling for trouble from beating and would need a relatively slow control loop. Multiple phase with shift can in theory get a faster control loop as the shifted phased allow faster reaction than a single converter stage.

The way the circuit is drawn uses another PWM to analog step to transfer the analog ouput of the error amplier to the stages. This additional dealy gives extra slow down and is not a good idea. There is no provisons for load sharing - more SMPS chips use a kind of PI control and thus chances are that 1 chip would tak over most of the load.

[ogden]

1. I wonder how PC motherboards (which have many so-called "phases" -- basically separate SMPSs running out of phase with each other to share the load and mostly cancel out the ripple) are wired up?

Multi-phase SMPS do not consist of separate SMPSs! All phases run from single conroller IC, using same frequency source, just phase angle of each phase is different.

Further reading: https://www.ti.com/lit/an/slva882b/slva882b.pdf

[Faringdon]

The way the circuit is drawn uses another PWM to analog step to transfer the analog ouput of the error amplier to the stages. This additional dealy gives extra slow down and is not a good idea.

Thanks, yes you are right...that is one of my dislikes of it.....but where that slow bandwidth can be tolerated it could be ok.
The slow bandwidth can unfortunately result in a high overvoltage when the load is suddenly turned off....so i was thinking of bringing in a comparator stage to slam off the converters whenever vout goes up to vout+5%, say.

The great thing about the PWM is that it can be made isolated by passing it through a digital isolater......this is a great thing, as chips like the UC3907 suffer when there are many paralleled modules as the large anlog loop is problematic for noise, not to mention, that the ground potential at each converter will be different.

Instead of isolators use simple solution known for more than 100 years, star ground.

Thanks yes, star grounding is good......though when the number of paralleled modules gets really high, then eventually it unfortunately becomes more impractical...and the ease of an isolated control signal, that doesnt care what  all the local grounds are at, seems attractive?

Running muplitple SMPs in parallel with deparate clocks is calling for trouble from beating and would need a relatively slow control loop.

Thanks, yes i agree, the beating is an issue...though with large-ish capacitor banks at the output of every smps, then it gets lessened a little.
Also, even   if there was beating, as you know, some loads can tolerate the overvoltage spike associated with the beating.

Multi-phase SMPS do not consist of separate SMPSs!

Thanks, your ti.com example is excellent. It does appear to be the best way to do multiphase controllers when number of phases is <6.
As you know, there are other multiphase bucks, eg, the linear.com ones, where they are literally 6 separate Buck smps's (phase interleave switched) acting as a multiphase system, into one common  load.
In the case of the linear.com bucks, they share current by literally connecting together their error amplifier outputs....and since they are transconductance error amplifiers they can indeed do this.
It does beg the question.....which is better for eg <6 phases?....

...Is it the linear.com system where they literally have 6 separate, individual  bucks acting together.?
...or is it the ti.com one where there is a single controller, and then 6 raw power stages?

And if there are many more than 6 phases, then  we must   consider  that another entirely different approach is needed altogether.

[T3sl4co1l]

What are the isolators and, whatever that is, PWM and filtering?? doing, everything is common ground just tie the CMPs, that's it.  Toss on a LT6909 or whatever to get phase sequence and there you go.

Even better, use a polyphase controller right out of the box. Downside, may be difficult to interface to higher output voltages; they tend to be made for specific use-cases, like CPU power.

Tim

[Faringdon]

What are the isolators and, whatever that is, PWM and filtering?? doing, everything is common ground just tie the CMPs, that's it.  Toss on a LT6909 or whatever to get phase sequence and there you go.

Thanks, yes, for that case, yes, you are correct.
Though sorry, as i have not explained myself well..

I am speaking of a system involving huge numbers of paralleled SMPS, (say 20+) where there is not a common ground, even though its all connected together, its so extensive, that it just isnt a common ground....then, thats when it appears the isolators etc are needed.

I think Ogdon, who very kindly  tells of the excellent ti.com chipset, would declare that when you have 20 or more smps's in parallel, then that ti.com chipset just isnt practical?

[Just_another_Dave]

What are the isolators and, whatever that is, PWM and filtering?? doing, everything is common ground just tie the CMPs, that's it.  Toss on a LT6909 or whatever to get phase sequence and there you go.

Thanks, yes, for that case, yes, you are correct.
Though sorry, as i have not explained myself well..

I am speaking of a system involving huge numbers of paralleled SMPS, (say 20+) where there is not a common ground, even though its all connected together, its so extensive, that it just isnt a common ground....then, thats when it appears the isolators etc are needed.

I think Ogdon, who very kindly  tells of the excellent ti.com chipset, would declare that when you have 20 or more smps's in parallel, then that ti.com chipset just isnt practical?

If a huge number of smps is required, some control ICs have a synchronization inputs. Additionally, phase shifting isn’t mandatory, but it reduces the required output filter, so achieving it might require generating the synchronization signal externally. On the other hand, each module should have a current loop to ensure that the output current is distributed equally between all of the converters. Then, a single voltage loop is used for all of them.

Another option consists in using a resonant topology able to operate in current source mode, but they’re more difficult to design than traditional topologies

[David Hess]

1. I wonder how PC motherboards (which have many so-called "phases" -- basically separate SMPSs running out of phase with each other to share the load and mostly cancel out the ripple) are wired up?

All of the examples I can think of use current mode control, so a single error amplifier is adjusting the peak current of each phase through a comparator.  But any current mode controller which provides access to its compensation pin can be used like this, including your example.

[Faringdon]

The amazing thing is, that you get load sharing chips like UC3907 and UC39002 that purport to be able to make a large array of smps’s all share output current, into a common load.
However, the Vicor DCM range does not use that method, and just uses “active Vout droop” to bring about sharing.
It kind of makes you wonder if the UC3907 and UC39002 are that good?…...i mean, why aren’t Vicor getting with it? Why does Vicor offer a completely different way of  doing it?

Vicor DCM power module
https://www.vicorpower.com/documents/application_notes/an_Parallel_DCMs.pdf

UCC39002
https://www.ti.com/product/UCC39002

[ogden]

...Is it the linear.com system where they literally have 6 separate, individual  bucks acting together.?
...or is it the ti.com one where there is a single controller, and then 6 raw power stages?

What are you talking about? Please provide pointer to linear.com design literally having 6 separate, individual  bucks acting together.

[ogden]

I think Ogdon, who very kindly  tells of the excellent ti.com chipset, would declare that when you have 20 or more smps's in parallel, then that ti.com chipset just isnt practical?

What?! 20 or more SMPS in parallel? Please describe application, state voltage and power.

[Faringdon]

What are you talking about? Please provide pointer to linear.com design literally having 6 separate, individual  bucks acting together.

I worked at a comms company who already had done it with 8 separate, individual bucks acting together....into the same load. It was using linear.com sync bucks,  each had a transconductance error amplifier and they just linked all their outputs together (the outputs of the EA's aswell as the buck outputs).

I forget the exact chip number....i will find it and get back.

The application then was  i think it was 12Vin and 0.8V out....and i think it was 70A or something.

20 or more SMPS in parallel?

Another way to have 20 or more smps in parallel, is just literally to shovel them in parallel, and make sure each one has a current clamp at its output...limiting it to its nominal max current output.........then you just hit the start button......they will share perfectly when on max load.....when not on max load, they wont share, but who cares...they are rated to carry their max load anyway.

BTW, i once put 12 vicor DCM modules in parallel to supply 3kW for 48v. Then they were going to take it forward to something like 40 in parallel to get higher power....but i was terminated after 3kw point as they thought they knew enough to go on from there.
Those DCMs had only "active vout droop" to make them share currnt...i also added a current clamp to each ones output. It worked fine.

[Faringdon]

As you know, the situation with multiple (large numbers of) paralleled SMPS is different when you cannot have  any droop in vout to facilitate sharing..
In that case. You need some sort of “load share bus”. This communicates with each SMPS controller individually, and adjusts each one so that all SMPS’s share current fairly equally.

IMHO, the recommended way is to measure each SMPS’s output current, and add them up to find the total current. You then know that each SMPS should be shipping a current of [I total]/n, where n is the number of SMPS’s paralleled. You then adjust, bit by bit, the individual Error Amplifier  (EA) reference voltages, until all the SMPS’s fairly well share current.

As you know, this cannot be done willy-nilly….one of the controllers must be assigned to be the “parent” controller. The others are its “children”, and will adjust themselves in accordance with it.This means that the parent must  start off with its EA reference  voltage being higher than all the others. (so that it definetely ships current) The others then adjust upwards, their reference voltage until all share current equally. This must happen continuously, and the data must be transmitted digitally, to avoid noise problems. At times, individual controllers will end up shipping too much current, and their reference voltage must be nudged downwards. Its an “iterative set and check” algorithm. [Shipping too much current?….Yes - > reduce reference voltage].
[Shipping too little current?….Yes - > increase reference voltage]

The iterations must be of a very low voltage value.

And all SMPS’s should have a current clamp on their output, such that its impossible for them to ship more then max_nominal_current/n.

There is one philosophy that says that the adjustment of the current output of individual SMPS’s should be done by a separately acting analog error amplifier. However, this is often not the case...because some modules require their current to be increased, and some require it to be decreased, so a single error amplifier cannot do the job.

This is so obviously the way to go that I cant understand why its not described anywhere on the internet?
Do you know why?

BTW, does anyone know why there are so few of these load share controllers, eg UC39002?
Why do so few people make them?

[David Hess]

The amazing thing is, that you get load sharing chips like UC3907 and UC39002 that purport to be able to make a large array of smps’s all share output current, into a common load.

It is easy to add current sharing with a current shunt and operational amplifier, however it requires access to the feedback network.

However, the Vicor DCM range does not use that method, and just uses “active Vout droop” to bring about sharing.
It kind of makes you wonder if the UC3907 and UC39002 are that good?…...i mean, why aren’t Vicor getting with it? Why does Vicor offer a completely different way of  doing it?

If the output tolerance is tight enough, then the output resistance provides enough ballasting to allow separate supplies to share current.

[ogden]

The application then was  i think it was 12Vin and 0.8V out....and i think it was 70A or something.

Most modern CPU voltage regulators for desktops/servers does that and more, using single multiphase converter. One I know: ISL6367

BTW, i once put 12 vicor DCM modules in parallel to supply 3kW for 48v. Then they were going to take it forward to something like 40 in parallel to get higher power....

How about 22KW @48V using just 11 modules? https://www.benning.de/nr-es/the-next-generation-slimline-telecom-power-supply-systems.html

[Berni]

Use a proper multiphase buck controller IC for this as others have said before.

Not only will current sharing not be a problem since there is only 1 error amplifier, but you also get benefits from the multiphase design where each phase takes turns in providing current, this drastically reduces the filtering capacitor requirements on the input and output.

Also you don't want to be using diodes in your power path at high powers. Take the extra cost of a synchronous buck design by adding another MOSFET or using one of those integrated high/low power output stages (PC motherboards love using those). Efficiency gets more important at high powers since it starts to cause heat dissipation issues and there is generally also a EMI benefit (That can also be an issue at high powers). The integrated power stage chips are nice because they contain a gate driver and also usually include some smarts to try and keep itself from blowing up such as overcurrent or overtemperature shutdown.