Power MOSFET (gate) ringing/oscillation

[notadave]

Here's a story that may make you re-think your stance:
...
"It's a transistor, it will read open circuit!" I asked him to humor me. It measured 2k.
...
The moral of the story is to not assume

The moral of the story is never to assume a device is working if the circuit is known not to work and no alternative hypothesis is available.
Good story. And yes, I know this happens. I myself never believe anything someone else tells me because I know it is always wrong and full of unstated assumptions. People also always ask for things they do not need because they are already going the wrong way.

[notadave]

Therefore I and possibly others will help you no further.
J.

That is ok and thank you for reading and considering.

[notadave]

What gate resistance are you using?  We use SiC MOSfets and we always make sure we can change the gate resistor value.  The low limit in the data sheet almost always gives us ringing problems. So we end up increasing the gate reisitor value to fix this problem.

Yes, that was my approach as well. We started with 15 Ohm and increased to 27 Ohm because it did help with one oscillation.

[temperance]

Maybe this can help:
https://www.infineon.com/assets/row/public/documents/24/42/infineon-mosfet-coolmos-gate-drivce-switching-dynamics-applicationnotes-en.pdf?fileId=5546d4626f229553016fb392d5e7749f

Edit: are you developing a phase shifted full bridge?

[David Hess]

There seems to be an oscillation during switching that is internal to the FET. From the outside it is most "visible" by measuring the gate voltage. I have observed it in the 30 to 100 MHz region.

...

Does this have a name?

I might describe it using the old term "Squegging".  Old tube television circuit circuits would refer to a "snivet".  Both are negative resistance oscillations although from different sources.  In the later case this was associated with "tetrode kink", where the transfer function has a negative differential resistance characteristic.  Bob Pease thought of it as a snivet:

For example, the first high-fidelity, all-MOSFET audio amplifier I ever saw blew up.  It worked okay in the lab, but some misguided engineer decided that if a bandwidth of 5 Hz to 50 kHz was good, then 0.5 Hz to 500 kHz was better.  Consequently, when the speaker cables were extended from 10 feet to 20 feet for a demonstration, the amplifier broke into a megahertz-region scream and promptly went up in smoke because of the lack of damping at the sources.  I was told that after a minor redesign the amplifier was perfectly reliable.  The redesign involved cutting the bandwidth down to a reasonable level, adding some ballasting in the sources, and tying anti-snivet resistors directly to the gate pins.  (Note: A snivet is a nasty, high-frequency oscillation originally found in vacuum-tube TV sets-an oscillation similar to the oscillation of a MOSFET with no resistance in series with its gate.)

The article I have posted in the forums several times now discussing emitter follower oscillations applies.  Capacitance at the source of the FET is reflected back to the gate producing a negative resistance.  Combine this with inductance in series with the gate connection and parasitic capacitance and oscillation becomes possible or even likely while the FET is switching through its linear region.

Although the voltages clearly exceed the maximum ratings there is no immediate failure. Thus the question is: Does this even matter? Obviously my employer will not accept "It does not seem to fail when I am looking." as a guaranty this will not cause a recall or worse.

Besides increasing power dissipation and becoming an EMI hazard, the oscillation can exceed the absolute maximum gate-to-source voltage rating, damaging or destroying the transistor.

I did catch this when I used a H near field probe to find the current path but could mostly find the signal around the device package not the PCB.[/size]

Jim William's current sniffing probe would be useful here.

When I looked at old designs I saw that most had, in parallel with the Gate-Source, a series capacitor-resistor. I did not know why, what problem they were supposed to solve.

There are several ways to treat this problem, including a series resistor or series resistor-capacitor snubber.

[notadave]

Maybe this can help

thanks

are you developing a phase shifted full bridge?

Na, just an electric servo motor drive that mostly works in bursts.

[notadave]

I have observed it in the 30 to 100 MHz

I must correct that statement.
The oscillations happen between 75 MHz and 140 MHz.
There is a resistor between the driver and the FET that does not carry the current that would be needed to cause the gate to have the observed voltages.

[mtwieg]

I have taken all of those into consideration. Many measurements have been made with multiple probes, oscilloscopes, ground connections.
I have not given the requested information on purpose as I know the train of thought and have no interest in following it. I have not come here to talk about layout inductance. I have stated that multiple times now.
Multiple engineers have looked at the problem. The layout was done by a seasoned now retired layout engineer with more than 30 years of experience.

Respectfully, I think I understand where you're coming from. We've all probably dealt with frustrating rabbit-hole problems, where by the time we turn to the outside world for advice we've already tried numerous experiments and scrapped many hypotheses, and we're not interested in re-litigating any of them. But that's exactly why it's important to share detailed info on what theories and experiments we've already tried, and provide detailed info about the design. Simply brushing off people's questions or suggestions because they're not going in the direction you want is going to make useful help much less likely. It's unfair to expect others to come up with a solution to a problem you're struggling with while only giving them a tiny sliver if the info you have access to.

Anyways, it's not clear if the circuit is actually unstable during switching transitions (that is, the oscillation will actually appear spontaneously even without fast transients perturbing the circuit) or if the circuit is merely underdamped and being perturbed by very fast di/dt or dv/dt. In the latter case, the solution is generally to reduce switching speed by reducing gate drive strength, adding snubbers, or selecting an entirely different device (like with a lower miller ratio). In the former case, reducing switching speed doesn't help, but adding snubbers or changing gate resistance can still help to tame the oscillation, and choosing a different device may help a great deal as well (maybe the distinction between the former and latter case isn't very relevant...).

I've seen many SMPS designs where ferrite beads are added to some of the legs of through hole MOSFETs, presumably to combat these sorts of issues. Sort of like the hair of the dog that bit you. I've never resorted to such a thing though, and IMO there's always a better solution than that.

[notadave]

We've all probably dealt with frustrating rabbit-hole problems, where by the time we turn to the outside world for advice we've already tried numerous experiments and scrapped many hypotheses, and we're not interested in re-litigating any of them.

You understood!  I have gone through this with a dozen engineers from other departments, other companies, my superiors. I have heard the same doubts, remarks, ideas multiple times.

But that's exactly why it's important to share detailed info on what theories and experiments we've already tried

True, I do not deny that.

provide detailed info about the design

There are limits to that, it is not a hobby project of mine. I can provide indirect generalized copies that do not allow deductions.

Simply brushing off people's questions or suggestions because they're not going in the direction you want is going to make useful help much less likely. It's unfair to expect others to come up with a solution to a problem you're struggling with while only giving them a tiny sliver if the info you have access to.

While I understand that I am looking for people with very specific experience, not help for my hobby by other hobbyists. I do not wish to waste other peoples time!
What I am doing here is waiting for "my future self", someone like me with the same issue.

it's not clear if the circuit is actually unstable during switching transitions (that is, the oscillation will actually appear spontaneously even without fast transients perturbing the circuit) or if the circuit is merely underdamped and being perturbed by very fast di/dt or dv/dt.

That is unclear because the situation is not that black and white.
There is a large spectrum of response intensities from 30V to 100V. Set the voltage to any threshold and wait long enough or load it hard enough and you will see the voltage U_GS.
The question can not be answered because there is no switching without switching.

ferrite beads are added to some of the legs of through hole MOSFETs, presumably to combat these sorts of issues.

Yes. I have heard of that too.

I've never resorted to such a thing though, and IMO there's always a better solution than that.

Just my position until now. I am out of other options.

[AnalogTodd]

Here's a story that may make you re-think your stance:
...
"It's a transistor, it will read open circuit!" I asked him to humor me. It measured 2k.
...
The moral of the story is to not assume

The moral of the story is never to assume a device is working if the circuit is known not to work and no alternative hypothesis is available.
Good story. And yes, I know this happens. I myself never believe anything someone else tells me because I know it is always wrong and full of unstated assumptions. People also always ask for things they do not need because they are already going the wrong way.

This is where your attitude is turning people away from actually wanting to help you. Don't believe something someone else tells you because it is always wrong and full of unstated assumptions? Then why are you asking for help? You know people are going the wrong way already, so why seek any assistance?

If my boss had not humored me in making that measurement, if he had been so confident as to say I was going the wrong way, I would have walked away. It wasn't something I was tasked with figuring out, it was his issue. I was trying to be helpful. I could have walked away and the root cause could still be unknown to this day. You've decided that my experience gives a different result than what you are putting forward, saying that the 'moral of the story' that I make in passing on to junior engineers I mentor is wrong. Have some humility.

Understand that when you come to someone for help with an issue, they are going to ask questions that support the most common explanations first. If you have reviewed those situations, show the evidence and people can move on to more esoteric possibilities. If instead you puff up your chest and act like any answer you get is wrong, people won't help.

[notadave]

This is where your attitude is turning people away from actually wanting to help you.

Do not mistake that for a lack of gratitude.

Don't believe something someone else tells you because it is always wrong and full of unstated assumptions? Then why are you asking for help? You know people are going the wrong way already, so why seek any assistance?

I was aware of that seeming contradiction. I am not interested in the same help that was forced upon me many times.
If the LLM AI can tell me about it, then I don't need to waste a human's time. The AI told me the same as all the humans did so far.

If my boss had not humored me in making that measurement, if he had been so confident as to say I was going the wrong way, I would have walked away. It wasn't something I was tasked with figuring out, it was his issue.

But what if your boss had already checked that transistor many times and found it defective every time?

Have some humility.

The trouble is that I have had 44-3 years of experience that tell me otherwise. Especially the last 5 years have been decremental for my humility.

Understand that when you come to someone for help with an issue, they are going to ask questions that support the most common explanations first.

I do, but I would not have come here if it were that simple. You seem to be a smart man, I came here to meet you and talk about that what isn't simple. The device I use is out of my control. I can randomly pick and test a different one, that is it. But as I noted, I assume this is a general issue, not one of this single device. In a way this FET is too good.
My first sentence was: "I am frustrated with power MOSFETs". I want it to switch but instead I get a linear operation as it is switching.

If you have reviewed those situations, show the evidence and people can move on to more esoteric possibilities.

• I have tested that it is not a common mode measurement artifact.
• I have tested that it is not an oscillation that involves the driver as there is no voltage drop over the gate resistor to support that hypothesis
• I have tested that the current is not flowing though the buffer capacitors
• Given the frequency and gate capacitance we can exclude any large inductance. Of course it may be a parasitic inductance in a n inductor.

[AnalogTodd]

I do, but I would not have come here if it were that simple. You seem to be a smart man, I came here to meet you and talk about that what isn't simple. The device I use is out of my control. I can randomly pick and test a different one, that is it. But as I noted, I assume this is a general issue, not one of this single device. In a way this FET is too good.
My first sentence was: "I am frustrated with power MOSFETs". I want it to switch but instead I get a linear operation as it is switching.

• I have tested that it is not a common mode measurement artifact.
• I have tested that it is not an oscillation that involves the driver as there is no voltage drop over the gate resistor to support that hypothesis
• I have tested that the current is not flowing though the buffer capacitors
• Given the frequency and gate capacitance we can exclude any large inductance. Of course it may be a parasitic inductance in a n inductor.

Let's see, we've got some basic ideas here now. You're not a power guy, you're an RF engineer:

Yes, that happens, but I am an RF engineer and the engineer in question had done power too, not just digital (Which trains the wrong intuitions/habits).
Other engineers that looked had experience in power and 400V DC high power.
We all know the difference between a loop with low area and a loop with large area. We triple checked. There are no dumb mistakes in the design.

What you've described in your posts is that you're driving a motor in bursts, absolutely a power consideration. We can tell you're not power, this is obvious from the phrase "I want it to switch but instead I get a linear operation as it is switching." Every power MOSFET transitions through the linear region as it goes from off to triode and back. That is one of the basic considerations in SMPS supplies and affects their efficiency.

So now there can be several questions that can be asked:

• You have talked about your switching frequency. What are the dV/dt rates of your drive signal and the drain of the MOSFET?
• How are you driving this servo motor? What protection is on it for when it switches off (snubber diode)?
• Does the high frequency only occur on one switch edge? Or is it on both transitions?
• Can you put a current probe on the drain or source to see how fast the current is transitioning in the MOSFET?

I'm leaning towards one or two ideas on this. One is the Miller capacitance of the MOSFET driving the gate up and down. You likely wouldn't see it on the other end of the drive resistor because of parasitic inductance that makes the resistor high impedance at that frequency.

The other is the parasitic inductance in the bond wires from the source lead of the FET to the die internally. With a high di/dt in the MOSFET you could be pushing the source up relative to the gate and causing oscillations there. Much less likely.

Either way, start thinking about actual construction of the MOSFET and the parasitic effects that are created.

But what if your boss had already checked that transistor many times and found it defective every time?

He had made measurements around it already dozens of times and had come to the conclusion that it was almost certainly something strange with the transistor, but nobody was able to figure out WHAT was actually wrong. Why? Because everyone was confident that it was a transistor and would act like a transistor. The measurement I suggested pointed not to the transistor per se, but instead to the daamaged oxide.

The trouble is that I have had 44-3 years of experience that tell me otherwise. Especially the last 5 years have been decremental for my humility.

I have decades of experience myself, but realize that someone else may know more in an area than I do. I've done power for almost all of those years. I'm not going to pretend I can design an RF mixer or power amplifier.  In the last few years I transitioned into doing design for radiation environments and am still learning new things from people who have experience in different areas than I have.

[mtwieg]

provide detailed info about the design

There are limits to that, it is not a hobby project of mine. I can provide indirect generalized copies that do not allow deductions.

Of course. Most useful info would be a snapshot of the PCB layout (either in CAD, or a photo of the PCBA), and some example scope captures of the waveform.

What I am doing here is waiting for "my future self", someone like me with the same issue.

Well anecdotally, I can tell you how I addressed a somewhat similar issue years ago. I was using power MOSFETs (meant for switching, in TO-3P packages) in a linear narrowband RF power amplifier (about 3MHz), and saw that when driven with a large enough amplitude, it would exhibit bursts of EMI at 130-160MHz. This wasn't a sustained oscillation, it happened when the drain current exceeded a certain level, then died down until the next cycle of the 3MHz waveform. I tried a few simple things like adjusting gate series resistance, adding RC snubbers to the drain and gate, etc, without much success. Ultimately what I did was build a very detailed spice model of the circuit. It started with fairly idealized components, then I added parasitic terms estimated from my PCB layout. Eventually the simulation produced the same behavior. Then I was able to use the simulation to determine an optimal solution, which worked well in the real circuit.

Of course, this approach requires very detailed knowledge of the circuit design, which you're not going to share.

provide detailed info about the design

There are limits to that, it is not a hobby project of mine. I can provide indirect generalized copies that do not allow deductions.

Of course. Most useful info would be a snapshot of the PCB layout (either in CAD, or a photo of the PCBA), and some example scope captures of the waveform.

Respectfully, it doesn't actually sound like there's anything novel about your application (half bridges driving a servo "in bursts"). Yet you are encountering a novel problem. That suggests that there is something peculiar about the design (probably layout or component selection). But there's no way for us to tell without more info.

The device I use is out of my control.

Well that's unfortunate. What is within your control? Do you expect us to guess at that too?

In a way this FET is too good.

Not sure what this is supposed to mean.

I have tested that it is not an oscillation that involves the driver as there is no voltage drop over the gate resistor to support that hypothesis

Not sure what this means. You said you observed this ringing on the gate, right?

I have tested that the current is not flowing though the buffer capacitors

By buffer capacitors, do you refer to the decoupling capacitors for the gate driver, or the half bridge itself? If the latter, what path do you think it's taking?

[David Hess]

Anyways, it's not clear if the circuit is actually unstable during switching transitions (that is, the oscillation will actually appear spontaneously even without fast transients perturbing the circuit) or if the circuit is merely underdamped and being perturbed by very fast di/dt or dv/dt. In the latter case, the solution is generally to reduce switching speed by reducing gate drive strength, adding snubbers, or selecting an entirely different device (like with a lower miller ratio). In the former case, reducing switching speed doesn't help, but adding snubbers or changing gate resistance can still help to tame the oscillation, and choosing a different device may help a great deal as well (maybe the distinction between the former and latter case isn't very relevant...).

A third possibility, at least in old power MOSFETs, is that high di/dt or dv/dt is triggering the parasitic NPN transistor causing all kinds of mayhem inside the power MOSFET.  Usually this would induce destructive secondary breakdown, but there are other odd things which can happen; avalanche behavior should have the potential to cause high frequency oscillation.

I thought modern power MOSFETs had long ago solved this problem, but I do occasionally still see maximum di/dt or dv/dt specifications in datasheets.

[uer166]

I've recently had a self-oscillating nMOS issue that was switched slowly on purpose. It had the right conditions to become a self-exciting Colpitts oscillator during certain parts of the turn on/off transition where the biasing was just right for that to happen; i.e. it wasn't normal LC oscillation.

Post the scope shots of Vgs, Vds, and stop wasting people's time, it's relatively obvious when this type of oscillation happens.

[temperance]

The other is the parasitic inductance in the bond wires from the source lead of the FET to the die internally. With a high di/dt in the MOSFET you could be pushing the source up relative to the gate and causing oscillations there. Much less likely.

You can't say that without knowing which MOSFET has been used. The transconductance of modern MOSFET's is extremely high. Those modern MOSFET's in DPAK and D2PAK with a couple nH (and even more) inductance in series with the source can be very hard to tame. Because of this, I switched to TOLL and similar packages with almost no inductance. And, when possible, with kelvin connected drivers to make them behave.


Are the MOSFET's you are using types with fast body diodes or "normal" body diodes?

[notadave]

To me it looks like a LCR with:
C = 1 nF
L = 1.5 nH (note that this does not fit large dimensions)
R = 1 Ohm
More specifically I suspect:
C = 1/(1/C_GS+1/(A*C_DG))
L = L_DS
R = R_G
Where in A is a voltage amplification increasing the Miller-Capacitance.
See attachment

[temperance]

What happens if the TO247 packages are not bolted onto a heat sink? I assume the heat sink is connected to 0 V and the stray capacitance between the TO247 and the heat sink is the source of energy.

[mtwieg]

To me it looks like a LCR with:
C = 1 nF
L = 1.5 nH (note that this does not fit large dimensions)
R = 1 Ohm
More specifically I suspect:
C = 1/(1/C_GS+1/(A*C_DG))
L = L_DS
R = R_G
Where in A is a voltage amplification increasing the Miller-Capacitance.
See attachment

I doubt you'll be able to simulate this issue without all three parasitic inductances and capacitances (it's unlikely that inductance in the FET's channel as you've drawn it will matter). Does the MOSFET vendor offer a spice model? Usually those will include package parasitics as well. For a TO-247 package, I'd expect the gate and source inductances to be 5-10nH each and the drain inductance to be 2-5nH.

[AnalogTodd]

I doubt you'll be able to simulate this issue without all three parasitic inductances and capacitances (it's unlikely that inductance in the FET's channel as you've drawn it will matter). Does the MOSFET vendor offer a spice model? Usually those will include package parasitics as well. For a TO-247 package, I'd expect the gate and source inductances to be 5-10nH each and the drain inductance to be 2-5nH.

A spice model and simulation might show quite a bit. I've spent a bunch of time going back through the posts made here describing what is being seen and there are notable items:

• The oscillations occurs during the switching time of the MOSFET. Once it has fully switched, the oscillation stops.
• It's driving a servo motor in 'bursts', and we have an idea of the burst frequency, but no idea of switch edge di/dt or dv/dt.
• Previous design versions had an RC on the gate-source.

The reason I asked these questions is to think about parasitic inductances and capacitances in the MOSFET and other devices around it. If the dv/dt on the drain of the MOSFET is very high, that's a lot of swing on the Miller capacitance of it and it can potentially drive the gate voltage up and down. Once the part has fully switched, no more di/dt or dv/dt and the problem goes away. If you add an RC on the gate, you now slow the switching down and the di/dt or dv/dt is controlled enough that the parasitics aren't as big of an issue.

[notadave]

if the circuit is actually unstable during switching transitions (that is, the oscillation will actually appear spontaneously even without fast transients perturbing the circuit) or if the circuit is merely underdamped and being perturbed by very fast di/dt or dv/dt.

I did not understand what you wanted, but now I think you are asking if the oscillation is dampened, attenuated.
Yes it is, but only moderately so. It does not start swinging on it's own!

recently had a self-oscillating nMOS issue that was switched slowly on purpose. It had the right conditions to become a self-exciting Colpitts oscillator during certain parts of the turn on/off transition where the biasing was just right for that to happen; i.e. it wasn't normal LC oscillation.
Post the scope shots of Vgs, Vds, and stop wasting people's time, it's relatively obvious when this type of oscillation happens.

If it is so easy why can't you describe it and let us know how one can tell? What do you need the graph for?
Would not a colpitts need a parallel LC in series with the gate? I don't see how that would be possible.

I do not understand why we can not talk about this on an abstract generic level? There must be a limited number of reasons, circumstances this can happen. I am not talking about 30 MHz here! We are talking over 100 MHz. Given that the gate is involved there might be an active component to this.

You can't say that without knowing which MOSFET has been used.

The devices we currently use are:
MOSFET  IPW60R099C7
Driver  2ED21844S06J

But we got other MOSFETs in the drawer.

What I find confusing is that the switching takes time but the oscillation can happen quickly enough within it.

I thought modern power MOSFETs had long ago solved this problem, but I do occasionally still see maximum di/dt or dv/dt specifications in datasheets.

We are well in specifications for that. No, I do not think it is that, but I suspect active behavior to be part of the problem, after all the gate source voltage does change a lot and U_DS does too.

What happens if the TO247 packages are not bolted onto a heat sink? I assume the heat sink is connected to 0 V and the stray capacitance between the TO247 and the heat sink is the source of energy.

Yes, the devices are isolated but close to a metal body, there is a Drain to 0V capacitance. Thank you for thinking of that. On the low side it is just adding to the C_DS, but for the high side this might be relevant.

I can tell you how I addressed a somewhat similar issue years ago. I was using power MOSFETs (meant for switching, in TO-3P packages) in a linear narrowband RF power amplifier (about 3MHz), and saw that when driven with a large enough amplitude, it would exhibit bursts of EMI at 130-160MHz. This wasn't a sustained oscillation, it happened when the drain current exceeded a certain level, then died down until the next cycle of the 3MHz waveform. I tried a few simple things like adjusting gate series resistance, adding RC snubbers to the drain and gate, etc, without much success. Ultimately what I did was build a very detailed spice model of the circuit. It started with fairly idealized components, then I added parasitic terms estimated from my PCB layout. Eventually the simulation produced the same behavior. Then I was able to use the simulation to determine an optimal solution, which worked well in the real circuit.
Of course, this approach requires very detailed knowledge of the circuit design, which you're not going to share.

And it would be crazy and impossible if you or anyone did the same from pictures of a 12 layer board with parts below metal blocks.
But your story is inspirational anyhow. A colleague did try to build a simulation but it does not show this behavior. Without some sort of 3D feature extraction, how did you estimate the parasitics? Very educated guessing, trial and error, measurements with a network analyzer? We are talking >>100 MHz here, not your average LCR-Meter.
Was it some sort of non-linear simulation that changed capacitance with voltage?
The trouble with that approach is that there is no guaranty of success, I might never see the oscillation, but if the effort/time is limited, then I could try/risk it.

The AI suggested a failure mode: The frequency could become so high that the current is not distributed evenly over the die. That might cause local over heating. This would explain why we do see failures sometimes but not always even though we do observe the gate oscillation.

The oscillations occurs during the switching time of the MOSFET. Once it has fully switched, the oscillation stops.

Yes

It's driving a servo motor in 'bursts', and we have an idea of the burst frequency

I could find out but the big busts are dictated externally thus are random for the circuit.
I don't see how it is relevant.

no idea of switch edge di/dt or dv/dt

I could provide ~2x estimates.
di/dt = 2A/ns
dv/dt = 7V/ns

Previous design versions had an RC on the gate-source

Yes, that is one thing we are trying. It worked, but not enough to stay in the max rating.

parasitic inductances and capacitances in the MOSFET and other devices around it.

When you do that then you should first think about the frequency an Quality factor and then what it would take to have that. Then you should test two different resistors and measure their impact on the time constant of the attenuation. I have done all that. I concluded that the inductance must be <10nH.

If the dv/dt on the drain of the MOSFET is very high, that's a lot of swing on the Miller capacitance of it and it can potentially drive the gate voltage up and down.

Yes, it always does.

Once the part has fully switched, no more di/dt or dv/dt and the problem goes away.

Right, but also both FETs are now fully ON or OFF.

If you add an RC on the gate, you now slow the switching down

Only a little. Do not over estimate the effect! While true in principle I doubt it is a sensible approach.

di/dt or dv/dt is controlled enough that the parasitics aren't as big of an issue.

That is common thinking.

My next Post will include some measurement pictures.

[notadave]

What happens if the TO247 packages are not bolted onto a heat sink?

The oscillation still happens. We have not systematically researched what, if anything, changes.

More attachments in the next post.

[temperance]

It seems the complete circuit itself is resonating at every switching edge and requires some work. Are you sure the gate source voltage you measure is the actual gate source voltage?

[mtwieg]

But your story is inspirational anyhow. A colleague did try to build a simulation but it does not show this behavior.

Really? I went ahead and set up a simple double-pulse test in LTspice using the vendor SPICE model, using an external 27ohm gate resistor (I arbitrarily set the bus voltage at 100V, not sure what you're using). Without doing anything else, the circuit exhibits extremely nasty oscillations, far worse than what you're seeing. In fact it's so bad I have to assume something isn't quite right with the spice model (maybe the damping resistors on the parasitic inductances need to be decreased). Simulation is attached.

[mtwieg]

Actually after tinkering with the LTspice model a bit, there's definitely something funky with the L1 model from infineon, I keep getting singular matrix errors, probably because one of the messy equations in the base cool_600_k1_var subcircuit keeps blowing up. The L0 model doesn't seem to have this issue, but it also has undamped parasitic inductors, which isn't realistic, so I added a Rdamp parameter to the L0 model. Also modified the inductance values for the L0 model to be the same as the L1 model. It still exhibits severe ringing on the gate, but not as insane as the L0 model.