Power MOSFET (gate) ringing/oscillation

[notadave]

sure the gate source voltage you measure is the actual gate source voltage?

Yes, we made very sure it is. At the moment there is a quarter of a million $ making sure it is.

[notadave]

Really? I went ahead and set up a simple double-pulse test in LTspice using the vendor SPICE model, using an external 27ohm gate resistor (I arbitrarily set the bus voltage at 100V, not sure what you're using). Without doing anything else, the circuit exhibits extremely nasty oscillations, far worse than what you're seeing. In fact it's so bad I have to assume something isn't quite right with the spice model (maybe the damping resistors on the parasitic inductances need to be decreased). Simulation is attached.

We use 220 to 330 Volt in the lab.
I did mention that a colleague did it and that my experiences at work were decremental to my humility.
I will have a look at the LTSpice sim. Thank you for now.

I did not make it explicit but there is no resistor on the source of any of the FETs, not even a few mili Ohm (shunt).

The Drain-Gate-Source and Drain-Source capacitances are not parallel to a large capacitor and thus see a relatively high impedance for transients.

This is a switching application, there is no intentional linear operation.

How are you driving this servo motor? What protection is on it for when it switches off (snubber diode)?

You mean when it brakes? There are large capacitors in the supply that rise in voltage, should the voltage rise too high there are TVS diodes that will start dumping until they die.

Does the high frequency only occur on one switch edge? Or is it on both transitions?

Both, it depends on the current.

Can you put a current probe on the drain or source to see how fast the current is transitioning in the MOSFET?

No, I did put a Rogowski coil on the source of one FET but that is simply mechanically difficult and the bandwidth is limited to 30 MHz. Measuring >100 MHz without shunt is not trivial.
Of course the effort for adding 50 or so milli Ohm may be justified, if we are asking a specific model based question, that is have a quantitative hypothesis to reject.

The Miller capacitance of the MOSFET driving the gate up and down.

That is always the case. What now?

You likely wouldn't see it on the other end of the drive resistor because of parasitic inductance that makes the resistor high impedance at that frequency.

There is a resistor there! I can see some current but it is not driving the action, it is following the gate voltage. I can not see it on the driver because the driver is driving.

The other is the parasitic inductance in the bond wires from the source lead of the FET to the die internally. With a high di/dt in the MOSFET you could be pushing the source up relative to the gate and causing oscillations there. Much less likely.

That is there, I measure it. What now? If the current is in the bond wires then it has to go somewhere, where? Why didn't I find it when I used the near field probe?

Either way, start thinking about actual construction of the MOSFET and the parasitic effects that are created.

More novel ideas. (sarcasm, yes.)
Do you know about the internals of these devices? I only have the datasheet and the official models, no further info on the structure, doping profiles, geometry, trenches, ...
I have a BA in semiconductors and an MA in Telecom/Radar. Yes, we did not focus on vertical super junction power devices. No, I am not familiar with the long form literature on them. I am looking for people who do. Are you one of them?

This feels like a game of Wack-them-all. Once you get rid of one oscillation another pops up. Today we observed a 170 MHz oscillation that coupled through a 1.5 uH coil capacitively.
I'd love to put 1 Ohm resistors everywhere.

I had an insight today:
If I add in parallel a series RC I can change both the capacitance and the dampening and more importantly I can measure the resistance that I am in parallel with. I can not measure all the resistors in the oscillator though. Even if I know the frequency and quality factor I can not easily calculate the L or C because I must not assume a pure series nor parallel LC oscillator.
I still think that it is useful to derive a 10x range that you suspect the values to be in.

[uer166]

From the traces and the nFET datasheet (took you long enough to provide relevant info), I can surmise:

It doesn't look like Colpitts, a Colpitts is possible in a single nFET when you have Cdg (the miller cap) + the gate drive inductance forming the parallel circuit. The traces don't "look" like that kind of oscillation but it's hard to be 100% certain.

What they do look like is diode hard recovery: you have current running through the body diode and you hard-switch it to the other leg. You mentioned that "di/dt = 2A/ns". That exceeds the datasheet abs. max by about 550%.

Superjunction FETs are terrible for hard switching, you'd be much better off with SiC or GaN. You can try slowing them down considerably by adding extra miller capacitance externally, but you will lose on efficiency.

Overall your traces show either terrible layout, terrible probing (you are using a optically isolated fiber probe with ~no loop hopefully, right?), or potentially running the FET well beyond what it's designed for.

If you suspect layout, start providing loop area estimates of the gate-source return path to gate driver, the common source inductance, and the Vbus decoupling inductance from the caps to the nFETs.

[uer166]

To demo how insane your di/dt is, yours is "di/dt = 2A/ns" = 2000 A/us. The datasheet for Irr says:

"27 A Irr for VR=400V,IF=9.7A,diF/dt=100A/µs"

So, the reverse recovery current that would need to be hard-stopped is 3x the nominal load current, at a di/dt that is twenty times lower than your operating point.

Unless this is a completely soft-switched topology with orders of magnitude slower di/dt, this is much too high for these nFETs. you will likely struggle even with SiC at these rates I think.

[uer166]

Third thing which would normally increase some margin here is related to the miller turn-on of the nFET that is off. The voltage induced on the nFET that is in the off-leg is way past Vgs_th, so if it is actually that high, that's enough to blow the whole bridge up.

The way to improve the margin (but not necessarily the oscillatory behavior) is 2-fold:

You use a split-output gate driver where the sink resistance is much lower than the drive resistance. That allows you to hold the nFET off harder than otherwise. Your gate driver has a single driver output so it can't do that. You can also create a diode-resistor arrangement but the Vf of the diode eats into the Vgs_th margin.

The second way is to have a negative off-drive (e.g. drive Vgs to -5V when off, instead of 0), this increases margin directly.

Neither of the 2 options above are a true fix, but you should be aware of those for a redesign.

[temperance]

I have taken all of those into consideration. Many measurements have been made with multiple probes, oscilloscopes, ground connections. I have not given the requested information on purpose as I know the train of thought and have no interest in following it. I have not come here to talk about layout inductance. I have stated that multiple times now.

So you are not allowed to think about:

di/dt
Source inductance, package and layout
What this combination does

Ignoring that, I'm going to write it anyhow: 2A/ns with 10 nH stray inductance equates into 20 V.


As mentioned by uer166, C7 MOSFETs are not meant for hard commutation.

https://www.infineon.com/assets/row/public/documents/24/42/infineon-application-note-600v-coolmos-c7-applicationnotes-en.pdf

While the data sheet of the device states hard switching, they are pointing at something different. Hard switching in the data sheet context refers to hard switching converters. (CCM PFC's, Two switch forward,...

Your application requires MOSFETs with fast body diodes suitable for hard commutation. The C7 series aren't meant for those applications with continuous hard commutation. (They do survive this. The reason is that in half bridge / full bridge converters hard commutation can occur temporarily under certain conditions like an overload. Older generations would just launch themselves into space after just a few of the commutation cycles.)

Super junction MOSFET body diodes and how they behave:
https://www.mdpi.com/2072-666X/16/11/1252

https://www.infineon.com/assets/row/public/documents/24/54/infineon-optimos-ensure-your-system-bodo-art-v01.00-en.pdf?fileId=5546d4614815da880148175a088b000d

As far as I know, only SiC MOSFETs are suitable hard commutation applications. Here is an example where it is specifically mentioned in the data sheet:
https://www.infineon.com/assets/row/public/documents/24/49/infineon-imt65r030m1h-datasheet-en.pdf

"Suitable for topologies with continuous hard commutation"

[uer166]

I did some searching for Si FETs with drastically different Qrr/Irr specs, and something like https://www.mouser.com/ProductDetail/ROHM-Semiconductor/R6042JNZ4C13?qs=2WXlatMagcGJR2crHh2ywA%3D%3D

Has only 20% Irr of the load current at the same di/dt test as C7, instead of 300%. Probably worth trying it out if you don't want to go to SiC, at the very least it will confirm the problem. From what I gather all major suppliers of SJ FETs will have similar issues so switching to SiC makes the most sense long term.

[mtwieg]

I have to echo the concerns from both uer166 and temperance regarding reverse recovery. I'm wondering how you estimated dt/dt=2A/ns. Even in my LTspice sim the di/dt was not that great (1.3A/ns). But even so it results in enormous reverse recovery current and charge (Irrm=55A). Either way, this is far faster than recommended in the datasheet. Even without the ringing, the power dissipation resulting from this will be substantial. Or maybe you have external schottky diodes already?

Superjunction FETs are terrible for hard switching, you'd be much better off with SiC or GaN.

Sure SiC/GaN is better, but I don't think there's any reason a MOSFET can't handle this. But yeah probably not this specific device family.

[AnalogTodd]

I miss a day and people really are able to dig into this further!

At the speeds that switching is trying to occur, one absolutely cannot ignore all of the parasitic effects that come into play. Wire and trace inductance can be 30nH/inch easily. A gate resistor starts looking like an inductor at some point, preventing the gate driver from seeing the signal at the other side of the resistor. With rise and fall times for the current of 2000A/us, the internal source bond wires on the MOSFET will cause it to rise 10V with the 5nH in the source (based on spice models). That's enough to turn the MOSFET off (or on based on switch edge) and the whole thing can easily sing at high frequency.

This likely won't be fixed by knowing doping profiles, trenches, geometry, etc. as much as understanding the mechanical construction of the device and the limitations that one should be following per the manufacturer datasheet. The TO-247 package has a large copper paddle that you can see by looking at the backside of the package. The die sits on this, with the drain electrically connected from the die backside. The gate and source connections are made with bond wires to the leads on the side which run along the paddle edge. Source bond wires are likely bigger diameter with many in parallel, while the gate wires come in from the opposite side. I know because I've dealt with parts being put in these packages. It's very unlikely to be a thermal effect as thermal time constants in silicon are in the msec range, not nsec.

The information from uer166, temperance, and mtwieg is all very relevant to the discussion here on how the information provided indicates improper use of the MOSFET, especially in regard to reverse current speeds.

[temperance]

Sure SiC/GaN is better, but I don't think there's any reason a MOSFET can't handle this. But yeah probably not this specific device family.

In the early days of commercial LLC and phase shifted full bridge converters the MOSFETs exploded seemingly at random during start up, overload or a fast change in operating point. With the evidence up in smoke, it was quite difficult to find what was going on. Around 2000 it became clear that the body diode was the problem. Some years later MOSFETs with improved body diodes to mitigate the problem became available. Although the body diodes of those early devices didn't fail as fast as those of the usual suspects, those devices are not meant for continuous hard commutation where the opposing body diode is being pulled out of conduction. They survive those conditions somewhat. But what "somewhat" means is very unclear (to me at least). There are some scary app notes on the subject available.

[notadave]

As mentioned by uer166, C7 MOSFETs are not meant for hard commutation.
While the data sheet of the device states hard switching, they are pointing at something different. Hard switching in the data sheet context refers to hard switching converters. (CCM PFC's, Two switch forward,...
Your application requires MOSFETs with fast body diodes suitable for hard commutation. The C7 series aren't meant for those applications with continuous hard commutation. (They do survive this. The reason is that in half bridge / full bridge converters hard commutation can occur temporarily under certain conditions like an overload. Older generations would just launch themselves into space after just a few of the commutation cycles.)
Super junction MOSFET body diodes and how they behave:
As far as I know, only SiC MOSFETs are suitable hard commutation applications. Here is an example where it is specifically mentioned in the data sheet
"Suitable for topologies with continuous hard commutation"

It will take me a few days to review the literature that I have downloaded.

[mtwieg]

While the data sheet of the device states hard switching, they are pointing at something different. Hard switching in the data sheet context refers to hard switching converters. (CCM PFC's, Two switch forward,...

I actually wasn't aware that hard switching and hard commutation were two distinct terms! Paying attention to this thread has already paid off for me. 

[uer166]

While the data sheet of the device states hard switching, they are pointing at something different. Hard switching in the data sheet context refers to hard switching converters. (CCM PFC's, Two switch forward,...

I actually wasn't aware that hard switching and hard commutation were two distinct terms! Paying attention to this thread has already paid off for me. 

Fun and distinct difference! This is partially why IGBTs are so attractive at high voltages: they have no inherent body diode, and you often see co-packaged antiparallel diodes with IGBT that have *much* better specs than a SJ FET body diode. There's even SiC diode / IGBT combos.

[notadave]

2A/ns with 10 nH stray inductance equates into 20 V.

Yes, one expert informed me that the TO-247 has more like >15nH per pin or adding 35nH to the loop.

Last week's shunt measurement revealed a peak of 140A of current during the oscillation.

As far as I know, only SiC MOSFETs are suitable hard commutation applications
...
"Suitable for topologies with continuous hard commutation"

Yes, given the voltage and application I would not use SJ MOSFET again but a SiC with Kelvin connection (extra pin).

The obvious thing that not a single person has mentioned anywhere (not in the literature, not in person, not in a forum):
The copper used to connect all the parts.
Had we used half the copper we might never have had any trouble.
And if the inductance were higher, not lower, we would not have >>100 MHz reaching >100A in nano seconds.
My colleagues even managed to find a configuration that would go >200 MHz and keep oscillating after the switching was over.
Bottom line is: Anything will resonate somewhere. These Super Junction FETs have a violent snap-off, that can not be controlled.
I would have to add 56mOhm to the source inside the gate loop to avoid the current peaks.

[notadave]

I am frustrated with power MOSFETs >200V_DS. They seem to like to oscillate in ways that are "illegal" compared to the datasheet.

I should have been more specific: Silicon Power MOSFETs.

When I talked to an application engineer from infineon I confronted him with the contradiction in the datasheets:
max(U_{GS_AC}) << L_S* max(di_S/dt)
For large packages it is simply impossible to get a compliant design as the switching is too fast and the resulting oscillation will do the rest.

[temperance]

I should have been more specific: Silicon Power MOSFETs.

When I talked to an application engineer from infineon I confronted him with the contradiction in the datasheets:
max(UGS_AC) << LS* max(diS/dt)
For large packages it is simply impossible to get a compliant design as the switching is too fast and the resulting oscillation will do the rest.

max(UGS_AC) << LS* max(diS/dt)

True. But you are using the wrong MOSFET in the wrong application.

Edit: If you would employ the MOSFET in question in a resonant supply, the problem stated does not exist. (only under overload conditions, making it difficult to check this. But that's another story)

The obvious thing that not a single person has mentioned anywhere (not in the literature, not in person, not in a forum): The copper used to connect all the parts.
Had we used half the copper we might never have had any trouble.

Given the supply voltage, I find that hard to believe. You need µH not pH.

But remember, we were not supposed to look at the board layout 

This might be of interest to you: saturable reactors:
https://www.niterramaterials.co.jp/en/product/am_parts_emc.htm

[notadave]

But you are using the wrong MOSFET in the wrong application.

And that is why I did not want to talk about the layout.

Given the supply voltage, I find that hard to believe. You need µH not pH.

I don't understand the context.

But remember, we were not supposed to look at the board layout

Yes, because it would have been a huge waste of time.

This might be of interest to you: saturable reactors

YES, they are. I tried to find them but could not.

[notadave]

I have to echo the concerns from both uer166 and temperance regarding reverse recovery. I'm wondering how you estimated dt/dt=2A/ns.

Very crudely. I knew what voltages I was measuring on the gate and I knew the order of magnitude of the inductance.

maybe you have external schottky diodes already

No, but we considered. The voltage is too high. SiC Diodes won't work either.

Sure SiC/GaN is better, but I don't think there's any reason a MOSFET can't handle this. But yeah probably not this specific device family.

That is what I thought but I have changed my mind.
I even took measures to work with the problem but they simply do not work at the frequency, too much capacitive coupling.

[temperance]

I don't understand the context.

The context is you stating to reduce the copper to connect all together. My guess for why you want to do that: reducing copper will increase stray inductance and reduce shoot trough current. Or is your statement pointing to something else like resistance at high frequencies caused by skin effects of a trace at 100 MHz and above?

I anyhow follow the following rule: for switching nodes, use the minimum amount of copper required and maximize the reference place.

Another remark if you switch to other devices:
The gate drive loop itself consisting of some capacitance and some stray inductance. An optimal gate resistors provides proper damping for the LC circuit. You can't control turn on / off times anyhow by selecting a gate resistor for SJ MOSFETs or SiC devices like it was possible for old generation MOSFETs because Crss drops to almost zero above very low voltages.

This feels like a game of Wack-them-all. Once you get rid of one oscillation another pops up. Today we observed a 170 MHz oscillation that coupled through a 1.5 uH coil capacitively.
I'd love to put 1 Ohm resistors everywhere.

That's the game, providing proper damping. At some company I'm being nick named Mr. 10R. I always have a few of those in my pockets for when the ferrite bead sprinkler crowd has done overtime again.

I have quite a bit of app notes on SJ MOSFETs:
https://www.infineon.com/assets/row/public/documents/24/42/infineon-applicationnote-650v-coolmos-c7-mastering-the-art-of-quickness-applicationnotes-en.pdf

Unfortunately I lost those witten by Fairchild in the early days (2002 and onwards). Maybe someone reading this still has those and would like to share them.

[notadave]

The context is you stating to reduce the copper to connect all together. My guess for why you want to do that: reducing copper will increase stray inductance and reduce shoot trough current. Or is your statement pointing to something else like resistance at high frequencies caused by skin effects of a trace at 100 MHz and above?I anyhow follow the following rule: for switching nodes, use the minimum amount of copper required and maximize the reference

Just for the resistance. Less copper, more dampening.

You can't control turn on / off times anyhow by selecting a gate resistor for SJ MOSFETs or SiC devices like it was possible for old generation MOSFETs because Crss drops to almost zero above very low voltages.

I don't understand. Their reasoning is about the R_G to C_GS relation during the plateau.

That's the game, providing proper damping.

True but that means power and that means heat in a lumped element that I have to show capable.

Mr. 10R. I always have a few of those in my pockets for when the ferrite bead sprinkler crowd has done overtime again.

That is what I do too! Those people just don't get that ferrites won't have 10 Ohm at the frequencies they are targeting. Then they get resonances or don't understand why the voltage keeps peaking. Stack 10 Ohm on top and the problem is gone.

I have quite a bit of app notes on SJ MOSFETs

Yes, I read that too. Over all, I was disappointed.

[uer166]

You mentioned that you want to increase inductances to reduce ringing: that doesn't work when you have an uncontrolled di/dt: it'll resonate and a lower frequency, sure, but the problem still exists.

In practice, you usually want to decrease the stray Ls until the Fresonant is so far away from the di/dt edge that it is no longer excited, hence why layout is so important.

SJ mosfet diode recovery is so darn fast that the layout would have to be extremely tight, potentially impossible with TH parts for that condition to exist, hence all the hacks with saturable nanocristalline cores etc. One thing you CAN control is the *other* FET di/dt switching speed and you should try reducing it until the reverse recovery peak current is drastically lower. Have you tried to do that?

Not all Mosfets are made equal too, the problem is well known and many manufacturers attempted to solve it in silicon, I gave you an example of a FET where I_rr is orders of magnitude lower than the C7 you used, did you have a chance to try it out?

Re: saturable reactors: I have tried to use them myself to solve this particular problem, but in my case the core losses were so high that they overheated and melted themselves, so it's not a slam-dunk.

As I mentioned before you can also try drop-in IGBT replacement that can have a very well behaved diode that is co-packaged with IGBT die.

[temperance]

About the miller plateau.

Old MOSFETs like an IRF840: Crss decreases gradually. You see a text book like miller plateau and the drain voltage du/dt changes at the same rate as miller capacitance changes.

SJ MOSFETs: the miller capacitance is very non linear and the change is very abrupt. The change in du/dt observed at the drain is just as non linear as Crss provided the gate current stays constant.

V_gs-plateau= V_gs(th) + I_D / g_fs

The non-linear part seen at voltages below 30...60 V has an advantage.

1. The MOSFET channel can be opened faster than the drain current is able to charge the output capacitance. Not all switching loss is in the channel but in charging the output capacitance. (For free, no snubbers. Something similar but not close in terms of losses can be achieved with Y5V capacitors drain to source.)
2. The du/dt becomes small near saturation and so does any di/dt.

The hard to tame disadvantage is the enormous g_fs where even the tiniest bit if source inductance will come after you. This g_fs did try to bite me when I used them for the first time. Because of that they are also difficult to handle when used into parallel. Some say ferrite beads (wash mouth with soap) in the gates will cure that. For dog lovers, It's uglier than a certain type of dog usually covered in sheep clothes during winters hiding most of its appearance.

Disappointing. At first yes, you want to hide behind the sofa for a while.

Re: saturable reactors: I have tried to use them myself to solve this particular problem, but in my case the core losses were so high that they overheated and melted themselves, so it's not a slam-dunk.

At which switching frequency? Or did the current still circulate at some very high frequency? I used them in a PFC about 25 years ago before SiC diodes became available.

[uer166]

At which switching frequency? Or did the current still circulate at some very high frequency? I used them in a PFC about 25 years ago before SiC diodes became available.

It was this thing: variable frequency and relatively large current: https://www.eevblog.com/forum/projects/experimental-48v-gt120vac-60hz-inverter

It's a weird case of both high voltage *and* high current.

[notadave]

you CAN control is the *other* FET di/dt switching speed and you should try reducing it until the reverse recovery peak current is drastically lower. Have you tried to do that?

No, but I should be able to double the R_G. It is a very crude method, but popular.
I started at 10 Ohm, then went up to 27. I might try 56 this week.

[temperance]

Sorry to pester/spam again. But taming the reverse current by adjusting the gate resistor of the opposing switch would keep me awake at night.

I think I shared it before. Reverse recovery current increases with increasing junction temperature.
https://pmc.ncbi.nlm.nih.gov/articles/PMC12654227/pdf/micromachines-16-01252.pdf

Something else. Littelfuse HiPerFET. They feature fast body diodes with half the reverse recovery current. According to Littelfuse short form literature those are fit for motor drive applications.

https://www.littelfuse.com/assetdocs/littelfuse-discrete-mosfets-ixfr80n60p3-datasheet?assetguid=009c6ff2-024a-4e5f-bfdb-8f99acaa6258

Other options/technologies are also available:
https://electronicscatalogs.littelfuse.com/Power-Semiconductor-Selection-Guide/26/

For the example shown, Crss is much higher and does not drop of a cliff with a 500/1 ratio as well, allowing for more control. I didn't check the other types.

Anyhow, I'm going to mind my own bussyness now. Let us know how it turned out.