Power On Reset not starting in reset

[EdT]

I find that my POR sometimes takes up to 10ms before it activates.
Green is power being applied.
Blue is reset going high, before going into the correct state.

[multipla]

Okay
And the question is?
Your schematic is unnecessary hard to read btw.

[Jeroen3]

From MAX6328 datasheet:

These circuits perform a single function: they assert a
reset signal whenever the VCC supply voltage declines
below a preset threshold, keeping it asserted for at least
100ms after VCC has risen above the reset threshold.

[EdT]

basically why this is happening and a way forward.  The reason it is happening is that the GND is not stable because we need to hot plug this and the POR wants a stable gnd.

[Jeroen3]

Usually hot swap uses a controller and power switch that turns on with a delay to ensure proper power supply sequencing.
It appears for a long time there is improper supply at this chip causing it to not work right, then it turns on and enables the delay.
It may even be possible the chip sees reverse polarity or ringing during the plug-in event, throwing it off even more.

The datasheet is vague about start up behavior, for example an STM1810 does specify start up behavior. indicating no operation of the open-drain output below Vcc(min).

Both both are not really suited a hot-swap controller imho.
Also the cpc1004n is an expensive part for this purpose.

It may also be the opto part is too sensitive with the reasonable high internal resistance of the reset switch.

[mtwieg]

From MAX6328 datasheet:

These circuits perform a single function: they assert a
reset signal whenever the VCC supply voltage declines
below a preset threshold, keeping it asserted for at least
100ms after VCC has risen above the reset threshold.

Yeah, but then it also says:

Active-Low Reset Output. RESET remains low while VCC is below the reset threshold and for at least 100ms after VCC rises above the reset threshold. RESET is open-drain on the MAX6328/MAX6348 and push-pull on the MAX6326/MAX6346.

Usually these sorts of chips spell out clearly how they react to a full power cycle but this one just... doesn't.

[Conventional Wisdom]

I know I'm late to this party, but the question about the behavior of power-on reset ICs is a common one.

>> Usually these sorts of chips spell out clearly how they react to a full power cycle but this one just... doesn't.

Actually, it does; the answer is in the Electrical Characteristics:  The minimum operating voltage is 1.0 V.  When Vcc is below this minimum, the output drive is undefined.  For an open-drain output device, the output will simply float to whatever voltage is being applied to it externally, e.g., through a pullup from Vcc.

A common way to generate a POR signal that is valid all the way down to zero Vcc is to choose an active-low reset, totem-pole output device and add a pulldown resistor to guarantee a low output below the device minimum Vcc.  Although the data sheet does not guarantee that the device won't inadvertently source current to the output when Vcc is below the minimum, I've never known that to happen in practice.

Regards -- CW