Is that showing all layers? Just 2 layers then?
There are many issues.
Planes are not well used, sacrificing the low inductance of opposite layers, instead joining both layers in parallel just to win a little more ampacity. You're better off using 3oz+ copper, or multilayer, to gain ampacity without sacrificing low inductance of a ground plane design.
The lack of planes also severely impacts EMI. The plane under the control/management section (bottom-right) means it will probably not affect function of the circuit itself, but it may well be loud enough to affect nearby circuitry.
This is also a problem endemic to the phase shift PWM scheme: the transformer is driven full wave in the common mode, even at zero power output (both phases in sync). Thus imposing a constant ping of 400V across the transformer's interwinding capacitance, every 75kHz. (Well, 150kHz, but alternating, so whichever. Or, when the two phases are shifted, twice that again really, where each contributes to its respective end of the primary winding.)
I've highlighted some illustrative examples:
1. The secondary side peak snubber is essentially irrelevant. Due to the narrow traces, long trace length, and circuitous return path, the total loop inductance here will be about 30nH. The 1A diodes aren't likely to appreciate the peak currents, either, assuming a capacitor large enough to matter -- which, 1nF is surely not enough.
The value of this snubber depends on the leakage inductance between the secondary halves. If the transformer is wound naively, then these will just be single layers/banks of wire (hopefully, litz cable!), and, what is that, three turns on a ETD49, so like half a meter of wire length each? In a typical transformer design (i.e. one not intentionally made extremely leaky), leakage inductance is proportional to wire length, so can be estimated quite easily in this way. A typical inductivity of 0.3uH/m applies, with the exact figure depending on the geometry (conductor width, spacing to other windings). So expect 150nH here.
The leakage inductance is relevant when the inverter applies differential voltage to the transformer. The primary side inductance is also involved, in a three-way network between source (inverter) and the two diodes (one staying on, one forced into reverse recovery), so the total inductance involved may be lower. When the inverter turns on, first loop current builds (to some amount greater than I_L2, because recovery is not instantaneous in PN junction types), then the one diode begins to turn off (current drops and voltage rises). The voltage continues to rise, overshooting due to these stray/leakage inductances, at a rate determined by drive strength, inductance, and node capacitance. So, for ballpark 150nH and 200pF, this will ring at around 29MHz. If driven to full magnitude (i.e. step change of 30A), this would develop a peak voltage of Ipk * sqrt(L/C) ~= 820V, plus transformer output voltage; likely due to inductances (like L1) and drive speed, the actual peak is lower, and well within the 600V rating of the diodes. Some damping to reduce ringing (i.e., R38, C30 -- R38 will probably be more like 22 ohms, I'm guessing these are placeholder values) will suffice.
Anyway, the peak clamp snubber (D22, D23, R36, C29) acts in parallel with this loop, at best reducing the inductance to ~30nH; an improvement, but not nearly as good as it can be. If moved to the edges between pours (transformer pins and nearby GND), this could be reduced to about 5-10nH, with the capacitors returned to GND because that's a supernode, and the resistor can be placed wherever, it doesn't participate in the high frequency loop.
2. Similarly for the inverter, Vbus and CS are extremely far apart, making an enormous loop. A bypass cap between Vbus and CS, directly in line between high side drain and low side source, would be able to solve this. But much better to redo the layout with 4 layers, interleaving Vbus, Passive, Active and CS all in the same place, with a bypass cap nearby.
3. What is C61 doing? Is that an EMI capacitor as suggested by its isolation remark? It's... there's a long, piddly trace connecting it back to the ground pour under the transformer/output capacitors. Alongside another ground trace, terminated beside it, going to I think the 12V/aux winding on the transformer?
Needless to say, any EMI filtering such a capacitor might provide, goes away entirely at rather modest frequencies. If its value is 4.7nF, the ~200nH stray trace inductance gives it a cutoff of a mere 200kHz, above which it's entirely inductive, and compared to the ~50 ohm impedances typical in EMI environments, will be of questionable utility by just a few MHz, and irrelevant by 40MHz (where XL = 50 ohm).
4. And what's up with the mounting? I see mounting holes for the TO-247s, I guess they'll be placed horizontally beneath the board, clamped against a heatsink. But there's no room for a screw head, there's traces top and bottom hugged right up against almost every hole. Will these be insulated with washers or something then? Maybe they're actually standing up, and bolted to heatsinks on top of the board. But then why waste so much layout area using an inappropriate footprint?
I'm afraid there isn't much I can do to help; the more I look at it, the more errors I find. And this is just a cropped-down section of the whole board. The only solution is a complete rip-up. Use 4 layers, and minimize loop areas. Recognize switching loops and place the respective components close together. Use appropriate rated components, and size EMI resistors and capacitors based on expected loop L/C. Layout extends up into the transformer as well: preferably, use a shield around the primary winding to absorb switching EMI, and use multiple layers of interleave, with bifilar secondary, to minimize leakage inductance.
Good luck,
Tim
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