Sanity check regarding transformer design, please

[Sniper1]

Why 24:5+5? and 30:6+6? my turns ratio would ideally be 6n:n +n and what you propose it like 5n:n+n i dont understand the logic.
Can you please explain why i should go for 5n:n+n and not 6n:n+n? what is your train of thought? Regarding winding loses, well it depndsTM i need to design and then use estimate ESR and parasitic to estimate loses

For your nominal conditions (Vin=400V, Vout=48V), that means your duty cycle would be 0.72 (referring to the secondary side). But you mentioned also wanting Vout up to 60V. And realistically you should be capable of operating at just 90% of your nominal Vin (to meet holdup time). So that would mean at worst case your duty cycle would be exactly 1.00. No headroom for handling load transients at all. Also if you plan on using a current transformer for sensing bridge current, you need to reserve some duty cycle for CT reset. And I assume you intend to use peak current mode control, in which case you want to avoid operating near 100% to make transient response faster. Using a 5:1+1 turn ratio should allow more headroom for such things.

Regarding safety yea and now, i did study some high voltage safety requirements but not for AC-DC specifically. I saw some planar transformer in some GaN USB chargers so why not ?

Sure it's definitely possible, but depending on what level of insulation you need (basic, reinforced, etc), you may need to drastically change the implementation of the windings.

As of now the most concearning part for me is the inductance value for the primary since there i messed up big time last time. Since it is PSFB leakage inductance is not a problem it is actually good up to some point.

True, PSFB is tolerant of more leakage inductance. Magnetizing inductance is important for maintaining soft switching under light load conditions though. In the worst case, if you Lmag is too high then you can put a large inductance in parallel with the primary to help.

Yea i totally forgot about 60V since i got scared of the core loses and went on a long optimisation path. In a way 5:1+1 mean less turn on the primary so easyer to design.
As for isolation my aim if basic (1500V)  but if i get it to be reinforced ( 3kv) then great , since for now this is a 1 off i have a few ways to make it better, with Kapton.
Anyway now alas i can take this transformer and resign the other parts, and i hope that untill the end of the mounth i can finish all the design work and order a PCB.

THX for the help
I am still a bit afraid of primary inductance but that may be just my PTSD from the past.
Ill post updates here as work progresses.

Hi

its been a while, i return to simulations and i am sort of stuck atm.
I modified your file so that it works with 390V dc input but i have 2 problems:
1) the SMPS seems to not start well
2) Vout is 12v not 48v tho this may be because it is not starting well

For 1) i suspect Overload is starting somehow since i saw current going over 710 mV, BUT for the transformer and resistors i used the TI calculator. I am still not sure what is the problem here but i suspect it is something regarding the current sense or input decoupling capacitance. I also tried to add a diode since that is like 0.5-0.7V of voltage drop but it did not help but Vout got a bit higher
2) might be because of 1) BUT i dont understand well the emulated optocoupler to begin with 

Any ideas?

[mtwieg]

I think you forgot to attach your simulation file(s)?

[Sniper1]

I think you forgot to attach your simulation file(s)?

OPS now i hope they are there

[Sniper1]

ok so i made another file and this time i used a real transformer for modelling and i got similar results.
I thought that the parallel 10k and diode will help but they did not.
Also it gets stuck at like 7.2ms then goes with 2-6us/s , also it generated 3GB of data.
So in a way the emulation you did was very good.

[mtwieg]

A few things I changed:
1. Changed all the power semiconductors to higher voltage ratings
2. Adjusted the snubbers (this seemed to make a big difference)
3. Adjusted the compensation network a bit
4. Increased the soft start caps (helps Vout settle faster)
5. Changed the model of D5 from a 3V LED to a 1.2V pn diode (helps prevent overshoot at startup)

Seems to work ok now. Feedback compensation still needs work. I tried to set up an FRA simulation but for some reason it wouldn't converge, seems to be an LTspice bug.

[Sniper1]

A few things I changed:
1. Changed all the power semiconductors to higher voltage ratings
2. Adjusted the snubbers (this seemed to make a big difference)
3. Adjusted the compensation network a bit
4. Increased the soft start caps (helps Vout settle faster)
5. Changed the model of D5 from a 3V LED to a 1.2V pn diode (helps prevent overshoot at startup)

Seems to work ok now. Feedback compensation still needs work. I tried to set up an FRA simulation but for some reason it wouldn't converge, seems to be an LTspice bug.

What is FRA?
I saw it its working even tried with 12 OHM load and it was not even noisy at the output. I didnt test transient loads but ill test that too.
found 2 problems:
1) there is a overshoot up to 60V at start up, i tried to play with SS capacitor didnt work but i didnt touch the opto coupler circuitry so maybe i can fix it from there
If the load is high this overshoot is lower at 4A it is 55V, probably some type of FB compensation problem
2) while checking the datasheet for the 100th time i noticed that the high side drivers work up to 100Vdc so i need to make some changes
the other controller chips are with encrypted models so that is a no go
There are half bridge gate drivers that i could put in the middle and yes they accept-20V input signals. Since they were probably designed for stuff like this.
Or i could try and use a gate drive transformer for the high side mosfets , never used something like this before but since the IC gate drive strength is 1.5A i think we can use the transformer directly
Also for primary side FET i was looking at this:
https://eu.mouser.com/datasheet/2/196/Infineon_IPL60R160CFD7_DataSheet_v02_01_EN-3362451.pdf
Tho it might be a bit overkill but not so many to chose from since there are a few that work at 500+V and there is also size and other parameters, for the isolated size am not sure yet might use same one or find something rated for 250-300V , technically i need 2*400/5=> 160V +20%=>192-20 but i see like 220-200V in the simulation and 20% over math seems about of ok , then again maybe there is something from diode reverse recovery or something.
What do you think?

[mtwieg]

What is FRA?

FRA stands for "frequency response analyzer," something that was added to LTspice in the last few years. Nominally it injects a stimulus into the feedback loop during a transient simulation, and automatically creates bode plots of the loop gain and displays stability margins. It's poorly documented though, and for some reason it doesn't work in this simulation... not sure why. But was hoping it could help with optimizing the compensation.

1) there is a overshoot up to 60V at start up, i tried to play with SS capacitor didnt work but i didnt touch the opto coupler circuitry so maybe i can fix it from there
If the load is high this overshoot is lower at 4A it is 55V, probably some type of FB compensation problem

Yeah the overshoot is bad. Likely just a matter of slowing down the soft start (making the simulation take longer), or optimizing the compensation, which is tedious since the FRA doesn't work...

2) while checking the datasheet for the 100th time i noticed that the high side drivers work up to 100Vdc so i need to make some changes
the other controller chips are with encrypted models so that is a no go
There are half bridge gate drivers that i could put in the middle and yes they accept-20V input signals. Since they were probably designed for stuff like this.

Sure for the real circuit you'll need some solution for gate drive. But the LTspice model probably doesn't care. I would hold off on making the simulation more complicated until you've answered your transformer concerns.

Regarding other models being encrypted, I actually wouldn't let that deter you from looking at other PWM controllers. As we can see, models from vendors aren't perfect. Personally, I would rather the manufacturer provide a clear description of how the controller works, enough that I can create my own simulation model from scratch. TI in particular often does provide sufficient details, though not always.

Or i could try and use a gate drive transformer for the high side mosfets , never used something like this before but since the IC gate drive strength is 1.5A i think we can use the transformer directly=
Also for primary side FET i was looking at this:
https://eu.mouser.com/datasheet/2/196/Infineon_IPL60R160CFD7_DataSheet_v02_01_EN-3362451.pdf

Those FETs would definitely be one of the best choices aside from SiC or GaN FETs. Nice thing about the PSFB is that, when designed well, you can get away without needing extremely good FETs.

For evaluating power semiconductors in simulation, I would abandon the LM5046 model entirely (slows things down too much) and instead just generate gate drive signals with arbitrary timings. Will make iteration much faster.

[Sniper1]

What is FRA?

FRA stands for "frequency response analyzer," something that was added to LTspice in the last few years. Nominally it injects a stimulus into the feedback loop during a transient simulation, and automatically creates bode plots of the loop gain and displays stability margins. It's poorly documented though, and for some reason it doesn't work in this simulation... not sure why. But was hoping it could help with optimizing the compensation.

1) there is a overshoot up to 60V at start up, i tried to play with SS capacitor didnt work but i didnt touch the opto coupler circuitry so maybe i can fix it from there
If the load is high this overshoot is lower at 4A it is 55V, probably some type of FB compensation problem

Yeah the overshoot is bad. Likely just a matter of slowing down the soft start (making the simulation take longer), or optimizing the compensation, which is tedious since the FRA doesn't work...

2) while checking the datasheet for the 100th time i noticed that the high side drivers work up to 100Vdc so i need to make some changes
the other controller chips are with encrypted models so that is a no go
There are half bridge gate drivers that i could put in the middle and yes they accept-20V input signals. Since they were probably designed for stuff like this.

Sure for the real circuit you'll need some solution for gate drive. But the LTspice model probably doesn't care. I would hold off on making the simulation more complicated until you've answered your transformer concerns.

Regarding other models being encrypted, I actually wouldn't let that deter you from looking at other PWM controllers. As we can see, models from vendors aren't perfect. Personally, I would rather the manufacturer provide a clear description of how the controller works, enough that I can create my own simulation model from scratch. TI in particular often does provide sufficient details, though not always.

Or i could try and use a gate drive transformer for the high side mosfets , never used something like this before but since the IC gate drive strength is 1.5A i think we can use the transformer directly=
Also for primary side FET i was looking at this:
https://eu.mouser.com/datasheet/2/196/Infineon_IPL60R160CFD7_DataSheet_v02_01_EN-3362451.pdf

Those FETs would definitely be one of the best choices aside from SiC or GaN FETs. Nice thing about the PSFB is that, when designed well, you can get away without needing extremely good FETs.

For evaluating power semiconductors in simulation, I would abandon the LM5046 model entirely (slows things down too much) and instead just generate gate drive signals with arbitrary timings. Will make iteration much faster.

i even doubled that soft start capacitor and i didnt help, tho i didnt do like x10 or something extreme like that , might do that at the end.

From what i see there are a lot of options from a lot of manufacturers, the fact that FSFB has ZVS helps a lot since i can use a worse gate driver IC. So in a way finding a driver is a non problem.
BTW i checked again how i was getting those huge voltages on the secondary: it was some spike at the rise of the signal, might not even be real IRL.

As for the controller I want to keep this one since i am not that good with spice so modelling another one is something i will find as a challenge in itself. Also professionally i have a few use case for this one 100Vdc is more then enough for a lot of non AC-DC stuff and the built in gate drivers are a great thing for simplified design.
As for the FET infineo provides a spice model ill add it to the simulation and see what happens , also I started on the PCB transformer design not sure what the leakage inductance will end up at but more is better up to a point , i am mostly after the DC resistance so i can better simulate the transformer .

Sic and GaN are a bit overkill for this power LVL and since this is a glorified toy / test platform ill stick to the traditional Si since i want something i worked with before and i already am taking a lot of steps in the unknown.

[Sniper1]

What is FRA?

FRA stands for "frequency response analyzer," something that was added to LTspice in the last few years. Nominally it injects a stimulus into the feedback loop during a transient simulation, and automatically creates bode plots of the loop gain and displays stability margins. It's poorly documented though, and for some reason it doesn't work in this simulation... not sure why. But was hoping it could help with optimizing the compensation.

1) there is a overshoot up to 60V at start up, i tried to play with SS capacitor didnt work but i didnt touch the opto coupler circuitry so maybe i can fix it from there
If the load is high this overshoot is lower at 4A it is 55V, probably some type of FB compensation problem

Yeah the overshoot is bad. Likely just a matter of slowing down the soft start (making the simulation take longer), or optimizing the compensation, which is tedious since the FRA doesn't work...

2) while checking the datasheet for the 100th time i noticed that the high side drivers work up to 100Vdc so i need to make some changes
the other controller chips are with encrypted models so that is a no go
There are half bridge gate drivers that i could put in the middle and yes they accept-20V input signals. Since they were probably designed for stuff like this.

Sure for the real circuit you'll need some solution for gate drive. But the LTspice model probably doesn't care. I would hold off on making the simulation more complicated until you've answered your transformer concerns.

Regarding other models being encrypted, I actually wouldn't let that deter you from looking at other PWM controllers. As we can see, models from vendors aren't perfect. Personally, I would rather the manufacturer provide a clear description of how the controller works, enough that I can create my own simulation model from scratch. TI in particular often does provide sufficient details, though not always.

Or i could try and use a gate drive transformer for the high side mosfets , never used something like this before but since the IC gate drive strength is 1.5A i think we can use the transformer directly=
Also for primary side FET i was looking at this:
https://eu.mouser.com/datasheet/2/196/Infineon_IPL60R160CFD7_DataSheet_v02_01_EN-3362451.pdf

Those FETs would definitely be one of the best choices aside from SiC or GaN FETs. Nice thing about the PSFB is that, when designed well, you can get away without needing extremely good FETs.

For evaluating power semiconductors in simulation, I would abandon the LM5046 model entirely (slows things down too much) and instead just generate gate drive signals with arbitrary timings. Will make iteration much faster.

i even doubled that soft start capacitor and i didnt help, tho i didnt do like x10 or something extreme like that , might do that at the end.

From what i see there are a lot of options from a lot of manufacturers, the fact that FSFB has ZVS helps a lot since i can use a worse gate driver IC. So in a way finding a driver is a non problem.
BTW i checked again how i was getting those huge voltages on the secondary: it was some spike at the rise of the signal, might not even be real IRL.

As for the controller I want to keep this one since i am not that good with spice so modelling another one is something i will find as a challenge in itself. Also professionally i have a few use case for this one 100Vdc is more then enough for a lot of non AC-DC stuff and the built in gate drivers are a great thing for simplified design.
As for the FET infineo provides a spice model ill add it to the simulation and see what happens , also I started on the PCB transformer design not sure what the leakage inductance will end up at but more is better up to a point , i am mostly after the DC resistance so i can better simulate the transformer .

Sic and GaN are a bit overkill for this power LVL and since this is a glorified toy / test platform ill stick to the traditional Si since i want something i worked with before and i already am taking a lot of steps in the unknown.

OK so i added the official FET model and with L0 model i get 0.67W poses on low side and 0.8W on the high side this like with the 4A load ( and a bit less in steady state operation)  . ( 7GB file...)
Whit these loses and no large thermal pad ill be at about 50C temp rise at 4A load so not that bad so i think ill heave heat problems + IRL i might bet more cooling with a the PCB design
L1 model seems to have convergence problems and to blame there is a current source from inside the controller model, might also be why the model is sort of slow .
L3 also does not converge because of the same node.
( Device Convergence Difficulty Score:
   u1:Gvref1    : 10.990991
   u1:Eosc3    : 1.711712 ) but runs without the start up option but ruin here is like 0.1ps/s or something like absurdly slow

in the controller model:
Gvref1         VCC REF TABLE { V(VREF3, REF) } ( (-0.7,-1)(0,0)(0.15,0.015) )  not sure why this is needed , might be some sort of ESD diode that is modeleld as a current source or something to do with some voltage reference
Also you can use the REF pin for optocouplker bias .

[Sniper1]

ok so i changed the diodes to the same FET but i cant get the system to be stable with synchronous rectification .
BTW that .71V voltage is soi that i can check CS pin vs a line and see where it was triggered.

And the driver is a random one since the synchronous rectifier outputs 5V signals, should still work but simulation was not happy
Probably was turning on to slow and entering linear region or something since i even saw negative voltages on the gates.

Any idea on how i can deal with the instability ? And or how to make the model begave with L1 L3 models for the FETS ?

[mtwieg]

I believe you've mixed up the drivers for the SR FETs.

Also, trying to make use of these Infineon models is going to make things very painful for you... Infineon creates their models to be accurate, not to be fast. Try using the alternate solver, if you haven't already. That should help, but these models will still be very slow.

Again, only make the simulation as complicated as it needs to be to answer the specific question you are asking. I don't think including synchronous rectifiers or realistic FET models are necessary to investigate transformer design (except maybe accounting for drain source capacitance).

[Sniper1]

I believe you've mixed up the drivers for the SR FETs.

Also, trying to make use of these Infineon models is going to make things very painful for you... Infineon creates their models to be accurate, not to be fast. Try using the alternate solver, if you haven't already. That should help, but these models will still be very slow.

Again, only make the simulation as complicated as it needs to be to answer the specific question you are asking. I don't think including synchronous rectifiers or realistic FET models are necessary to investigate transformer design (except maybe accounting for drain source capacitance).

Yea i inverted the SR signals and it works much better now.
Normal solver seems a bit faster.
After i corected the SR signals it works with 1A load but it did not with 4A load. Trying a few things now , increasing the SS cap since CS pin experienced a overload* current.
tho i have a few other leads too.
BTW yea simulation time is long but often i also work in kicad or at something so it is not that bad

[Sniper1]

ok i am sort of sure now it is something from the CS pin since that is the only thing that systematically entered error* mode.
I have no idea why TI xcel calculates with 75% or resistor needed for max current .
Application note tells us to mat it so that it is like 0.2V under threshold.
RC filter that goes to CS pin seems not to help, neither increasing that 1nF cap that is a filter .
Also transformer primary will be like 1 ohm and i also added that in the simulation, nothing important changed.
Ill see what resistor value i end up with and also try that.
Good night.

PS resistor did the trick at least with a quess value, xcel said 60 ohm i tried 40 ohm and it was ok

[Sniper1]

In current mode control i noticed there is somewhat a discrepancy between how the current sense load resistor in calculated between the UCC application note and TI XLS calculator. For me it is 60ohm using XLS ( here it is 75% of ideal* steady state resistor for max current) .
IF i use the formula form the UCC28950 ( also change the peak current on CS pin voltage value from 2V to .75V) then i get 38.5 OHM.

But for the LM5046 the slope is with current 0-100uA through slope resistor R13 in XLS and that translates to 0.24V for me , and if i do the math with this value i get 35.66 OHM.

I tried and simulated with 36 OHM and it was all good even at max load. Also i changed the compensation a bit and got rig of that large overshoot and now i have a monotonic ramp up.
ill also try with 39 OHM and see how it behaves.

And now i think ill focus a bit more on the real schematic and maybe replace the FB circuit with a simple opto model since i sort of need to tun the FB+comp for a certain opto

[Sniper1]

I believe you've mixed up the drivers for the SR FETs.

Also, trying to make use of these Infineon models is going to make things very painful for you... Infineon creates their models to be accurate, not to be fast. Try using the alternate solver, if you haven't already. That should help, but these models will still be very slow.

Again, only make the simulation as complicated as it needs to be to answer the specific question you are asking. I don't think including synchronous rectifiers or realistic FET models are necessary to investigate transformer design (except maybe accounting for drain source capacitance).

OK so when building a real FB circuit i hit  a real WALL: i dont understand ho it works  :'( .

Regardless if it is at 1A load or 5A load Voltage at comp in is about .9V and the current through the FB diode is about the same.
Worst of all i have no idea how you set it all up on the primary side , on the secondary i sort of understand the standard circuit .

Well datasheet is also not great from what i understand 1mA corresponds to 0% duty cycle but no data on that is 100% duty cycle
Could you please demystify the FB for me

[mtwieg]

OK so when building a real FB circuit i hit  a real WALL: i dont understand ho it works  :'( .

Regardless if it is at 1A load or 5A load Voltage at comp in is about .9V and the current through the FB diode is about the same.
Worst of all i have no idea how you set it all up on the primary side , on the secondary i sort of understand the standard circuit .

Well datasheet is also not great from what i understand 1mA corresponds to 0% duty cycle but no data on that is 100% duty cycle
Could you please demystify the FB for me

The datasheet is fairly transparent regarding this, see the functional block diagram, and section 7.3.8:

The COMP current is fed to a current mirror, the output of which connects to the 5V REF via a 5K resistor. In the subcircuit, this is node COMPI. So this voltage will be V(COMPI) = 5-1000*I(COMP).

COMPI is is also clamped by the SS pin voltage, so in reality you get V(COMPI) = min(V(SS), 5-1000*I(COMP)).

Some more circuitry then reduces COMPI, first by subtracting 1V from it, then cutting it in half with a resistor divider. The result (node COMP2PWM in the model) is what is applied to the inverting input of the PWM comparator. The noninverting input to this comparator is the RAMP pin, which comes from your current sensor. Basically, power will be delivered to the transformer until V(RAMP) = V(COMP2PWM). Or, putting all those equations, V(RAMP) = (min(V(SS), 5-1000*I(COMP)) - 1.0)/2. This all may look bizarre, but I've seen the same sort of circuitry used in many PWM converters.

One thing to keep in mind is that the datasheet describes ways to use the chip for pure voltage-mode control (I(COMP) directly controls duty cycle) or current-mode (I(COMP) controls peak transformer current). Which control mode is used depends on how the RAMP pin is connected.

In the case where the RAMP pin is connected to a sawtooth waveform with constant slope (i.e. from the SLOPE pin, not from your current sensor), then you end up with is pure voltage-mode control. Figure 17 also shows a way to generate the ramp from Vin, which provides some useful feedforward compensation (but it's still voltage-mode).

In the case where the ramp pin is only connected to your current sensor (no connection to the SLOPE pin), then you instead end up with simple peak current-mode control.

However, with current mode control you will run into subharmonic oscillations when operating at duty cycles above 50% (in continuous conduction mode, that is). The fix for this is to inject some fixed sawtooth waveform into the current-sense signal. This is shown in fig 11 of the datasheet. Basically what you end up with is a combination between pure current mode and pure voltage mode control. The higher the duty cycle you operate at, the stronger your slope compensation must be. The stronger the slope compensation, the stronger the influence of the voltage-mode control. This was one of the reasons I was suggesting you change turns ratio, so that you don't have to operate near 100% duty cycle.

Also, these tradeoffs are not something particular to the LM5046, or to this SPICE model. Same thing will apply to 99% of PWM controllers (excepting some that use very esoteric control schemes).

[Sniper1]

OK so when building a real FB circuit i hit  a real WALL: i dont understand ho it works  :'( .

Regardless if it is at 1A load or 5A load Voltage at comp in is about .9V and the current through the FB diode is about the same.
Worst of all i have no idea how you set it all up on the primary side , on the secondary i sort of understand the standard circuit .

Well datasheet is also not great from what i understand 1mA corresponds to 0% duty cycle but no data on that is 100% duty cycle
Could you please demystify the FB for me

The datasheet is fairly transparent regarding this, see the functional block diagram, and section 7.3.8:

The COMP current is fed to a current mirror, the output of which connects to the 5V REF via a 5K resistor. In the subcircuit, this is node COMPI. So this voltage will be V(COMPI) = 5-1000*I(COMP).

COMPI is is also clamped by the SS pin voltage, so in reality you get V(COMPI) = min(V(SS), 5-1000*I(COMP)).

Some more circuitry then reduces COMPI, first by subtracting 1V from it, then cutting it in half with a resistor divider. The result (node COMP2PWM in the model) is what is applied to the inverting input of the PWM comparator. The noninverting input to this comparator is the RAMP pin, which comes from your current sensor. Basically, power will be delivered to the transformer until V(RAMP) = V(COMP2PWM). Or, putting all those equations, V(RAMP) = (min(V(SS), 5-1000*I(COMP)) - 1.0)/2. This all may look bizarre, but I've seen the same sort of circuitry used in many PWM converters.

One thing to keep in mind is that the datasheet describes ways to use the chip for pure voltage-mode control (I(COMP) directly controls duty cycle) or current-mode (I(COMP) controls peak transformer current). Which control mode is used depends on how the RAMP pin is connected.

In the case where the RAMP pin is connected to a sawtooth waveform with constant slope (i.e. from the SLOPE pin, not from your current sensor), then you end up with is pure voltage-mode control. Figure 17 also shows a way to generate the ramp from Vin, which provides some useful feedforward compensation (but it's still voltage-mode).

In the case where the ramp pin is only connected to your current sensor (no connection to the SLOPE pin), then you instead end up with simple peak current-mode control.

However, with current mode control you will run into subharmonic oscillations when operating at duty cycles above 50% (in continuous conduction mode, that is). The fix for this is to inject some fixed sawtooth waveform into the current-sense signal. This is shown in fig 11 of the datasheet. Basically what you end up with is a combination between pure current mode and pure voltage mode control. The higher the duty cycle you operate at, the stronger your slope compensation must be. The stronger the slope compensation, the stronger the influence of the voltage-mode control. This was one of the reasons I was suggesting you change turns ratio, so that you don't have to operate near 100% duty cycle.

Also, these tradeoffs are not something particular to the LM5046, or to this SPICE model. Same thing will apply to 99% of PWM controllers (excepting some that use very esoteric control schemes).

THX most of i i did understand but how to implement in practice this with real components in my problem.
And yes it is very odd when u see it coming from mostly LDO buck SMSP

I also read that 0 current through COMP pin is 100% duty cycle or what is practical max
And 1ma through COMP pin is 0% duty cycle.
The part that scares me the most is the real optocoupler since as of now i only managed to make them work in a digital signal context and  the other isolated SMPS i made did not work at all so this is primarily from where i am coming.

On the non isolated part i only have a pull up resistor that i need to tune a bit but the other side is what waries me since i saw how much compensation can change start up .

I found some resources to study but i am still reading. Ill post my final circuit after i am done.
As o f now i am looking at opcouplers , do u happen to know a few part numbers with public SPICE models or where i can find something about the compensation network that they need?
As for the main transformer i am not done with layout or rather i am not satisfied but it is slowly taking a nice shape

[mtwieg]

Optocouplers are a completely different can of worms. I'd suggest making a new topic, maybe in the Beginners or Projects subforums. I'm not an expert on optos and you'll probably get more answers that way.

[Sniper1]

Optocouplers are a completely different can of worms. I'd suggest making a new topic, maybe in the Beginners or Projects subforums. I'm not an expert on optos and you'll probably get more answers that way.

I will ask in another thread. Transformer primary is sort of done, with what i think is enough isolation.
Now doing main PCB where ill have the aux windings and the secondary.
When i am done with that too ill improve the simulation tho beside the opto i am sort of close anyway and 300 mOHM more then what i simulated with ( 1 OHM ) connections will probably add mode so i am sort of confident here.
Well this is all according to Saturn PCB calculator..... sot at max load ill need to dissipate about 2W
This is JLC 0.5 OZ copper on internal layers if i go for 1 OZ then my loses will be about 1W , this is DC resistance.
at my 250 KHz skin depth is 132 um so if i use 1 or 0.5 OZ should still matter since 1 OZ is 35 um so i think it will be fully utilised.
As for leakage inductance i have no idea what i will get. 

[mtwieg]

When i am done with that too ill improve the simulation tho beside the opto i am sort of close anyway and 300 mOHM more then what i simulated with ( 1 OHM ) connections will probably add mode so i am sort of confident here.
Well this is all according to Saturn PCB calculator..... sot at max load ill need to dissipate about 2W\
This is JLC 0.5 OZ copper on internal layers if i go for 1 OZ then my loses will be about 1W , this is DC resistance.
at my 250 KHz skin depth is 132 um so if i use 1 or 0.5 OZ should still matter since 1 OZ is 35 um so i think it will be fully utilised.

I don't think SaturnPCB is going to be very helpful for designing the transformer windings (unless they added some fancy new features recently). You may want to review literature regarding winding design:
https://www.ti.com/download/trng/docs/seminar/Topic4LD.pdf
http://focus.ti.com/lit/ml/slup198/slup198.pdf

Keep in mind that there are different strategies for winding optimization for different design objectives. For example, some strategies prioritize lowest leakage inductance, while others may prioritize lowest interwinding capacitance. Don't adopt a method unless you know it fits your application (the interleaved approach in the first link above is probably a good start).

As for leakage inductance i have no idea what i will get. 

For you I would suggest not trying to make the transformer provide all the leakage inductance required for soft switching. Shoot for a lower leakage in the transformer, and add an external inductor to provide most of the effective leakage. This makes the design process much more forgiving.

[Sniper1]

When i am done with that too ill improve the simulation tho beside the opto i am sort of close anyway and 300 mOHM more then what i simulated with ( 1 OHM ) connections will probably add mode so i am sort of confident here.
Well this is all according to Saturn PCB calculator..... sot at max load ill need to dissipate about 2W\
This is JLC 0.5 OZ copper on internal layers if i go for 1 OZ then my loses will be about 1W , this is DC resistance.
at my 250 KHz skin depth is 132 um so if i use 1 or 0.5 OZ should still matter since 1 OZ is 35 um so i think it will be fully utilised.

I don't think SaturnPCB is going to be very helpful for designing the transformer windings (unless they added some fancy new features recently). You may want to review literature regarding winding design:
https://www.ti.com/download/trng/docs/seminar/Topic4LD.pdf
http://focus.ti.com/lit/ml/slup198/slup198.pdf

Keep in mind that there are different strategies for winding optimization for different design objectives. For example, some strategies prioritize lowest leakage inductance, while others may prioritize lowest interwinding capacitance. Don't adopt a method unless you know it fits your application (the interleaved approach in the first link above is probably a good start).

As for leakage inductance i have no idea what i will get. 

For you I would suggest not trying to make the transformer provide all the leakage inductance required for soft switching. Shoot for a lower leakage in the transformer, and add an external inductor to provide most of the effective leakage. This makes the design process much more forgiving.

THX but i already read them , i did a refresh now and it seems ok, my copper is on the low side but there again i have a thinner PCB so it can sort of cool easier but also lower thermal mass.
So it should be ok but might get hotter... Then again depending on how it goes it well get used in another revision.
Now it is mostly DIY hobby from 3 PCB so it is cheaper at JLC but if i go with a more serious design i might need to actually quote different combinations to see what is cheaper
But it needs to run in the first place and run ok, hot is good enough since it is on a budget
Anyway probably for the rest of the month ill figure the main PCB and other parts.
As for leakege inductance ill measure it after i make it, if i expect it to be like in the simulation .99 coupling then it is 60uH but ill leave a footprint for a discrete iductor since this is a wild guess ( ill calculate what i need exactly overall later)

[Sniper1]

Transformer PCB arrived ,
After a large pause i am back at it.
Apparently simulations were super slow since there was a very large occasional current spike probably due to artefacts since it is independent of mosfet used or deadtime.
Transformer ESR for V1 is 2 OHM ( ordered with 0.5 ox copper on inner layers by mistake).
I am yet to test the inductance. I need to remember how i did it with a resonat tank.
It is high but for now mostly  testing to see how was my inductance math.