Sanity check regarding transformer design, please

[Sniper1]

So this is my first time designing a high power transformer, last time it was like 10 W and i was like way off in terms of inductance ( math was off ).

So i am posting here since this time this is way more dangerous and it is in a larger design so i am sort of want to have something at least functional this time, first try maybe not full power maybe not full voltage range but at leat to work at nominal at lets say 50% . Last time i had like 1/2- 1/3 the inductance i needed and tons of leakage inductance and it ended in a mess.

So here is the design details:

topology Full bridge 500 kHz switching ( so fets work at like 250kHz) transformer is planar design

Vin 300V+ mostly 380-410vDc 390Vdc nominal ( 300vdc since it will start with that and then powers the APFC stage that gives 390v nominal, the APFC stage works and it was tested a bit already in another design)

Vout 48V nominal maybe 55-60V to compensate cables @ 5A ( i would be happy with 1A min first try)

On the secondary i will have a centre taped winding and there is a bias winding that feeds the APFC with about 12 V ( it accepts max 22v but i sort of need 10.5-11.5 min to be same so maybe 12 is a bit to close )

So according to my math at nominal i would need 6: 1 :0.25 transformer or rather 24 pri / 4 sec / 1-2 aux

According to TI datasheet i would need about 2.5 mH. So i want to did the math for a ton of cores that fit my size restrains and are available online.

Here is what i ended up with : EI Core: ELP 22/6/16 Material: N95

https://www.tdk-electronics.tdk.com/inf/80/db/fer/elp_22_6_16.pdf

https://www.tdk-electronics.tdk.com/inf/80/db/fer/elp_22_6_16.pdf


why N95 , because the winding number looked great on paper : 20.2 → 20 3.4 → 3

BUT if i round up i get 22 / 4 ( 5.5 / 1 ratio ) and that looks way better since it can be made symmetrical and have 2 winding per layer.

IF i redo all the math in reverse i get 2.95 mH primary inductance with

Bpeak​=Np​⋅Ae​V⋅ton​​

Bpeak=400⋅1×10−622⋅78.5×10−6=4001.727≈0.232 T

Bpeak​=22⋅78.5×10−6400⋅1×10−6​=1.727400​≈0.232 T​

So i dont think it will saturate

BUT now my ratio is 5.5/1 i am not sure if this is ok on one hand yea i can compensate a bit more in terms of loses but then again will i even have loses that big?

So here is the alternative: 24 / 4 here i keep the ratio and increase the primary winding number.

So here is what i get ( with the same core and material) :

Lp​=Np2​⋅AL​=242⋅6100=576⋅6100=3,513,600 nH=3.51 mH​

Bpeak​=Np​⋅Ae​V⋅ton​​=24⋅78.5×10−6400⋅1×10−6​=1.884400​≈0.212 T​

More inductance on the primary should be a good things since it will theoretically enable me to lower my switching frequency or deliver more power. but for now ill be very happy to just get part of what i design for.

So here is my dilemmas:

A) Should i use 22 or 24 wingdings on the primary? I sort of excluded 23 since i cant get that with a symmetrical transformer design . Or maybe have 23 and also have the bias winding on that layer instead of an additional primary winding?

B) Regarding the aux i am again not sure if i should use 1 or 2 winding, 1 m,ay be to little to power my APFC but 2 is a bit to much tho i can use a resistor and zener to clamp it to 20 V ish but i am afraid not to make a heating element . Here i am sort of leaning heavily on 2 windings but i am still sceptic since it is low power i have a bit more options.

C) What PCB trace width should i use for the transformer ? Should i go with 1mm/ 1 Arms?

D) Am i even close to reality? Last time i was way of in winding number ( tho then i had air gap and that might have also been part of my problems since i might have also added extra air gap with glue.

NOTE: Transformer is planar since i have 10 mm height for the entire design due to mechanical constraints ( and it also helps with electrical safety since it is easier to check since stuff is not touching randomly).

I find it easier to design and it sort of makes me feel safer, since hand winding something like that makes me super nervous and 400 Vdc is SUPER DANGEROUS.

With that core i have 3.2 mm so basically 2 PCBs will have all the windings, based on width i think i can get away with 6-8 layers per PCB .

Sorry of my tone sounded sad or to pessimistic, i am just coming from a few failed designs and i sort of lost my confidence + this time the voltages are also dangerous so there is even less margin for error.

THX in advance for your help.

[mtwieg]

There's a lot to go over there, I'll just start with the turns ratios.
You mention using a center tapped secondary. Therefore with a 6:1 turns ratio, the voltage ratio will actually be 12:1, so with a 400V primary you can't possibly get 48V out.

Even with full wave rectifier on the secondary side, a 6:1 turns ratio does not leave you with much headroom for responding to transient conditions.

Do you have a holdup spec? That can also necessitate more headroom on turns ratio.

Vin 300V+ mostly 380-410vDc 390Vdc nominal ( 300vdc since it will start with that and then powers the APFC stage that gives 390v nominal, the APFC stage works and it was tested a bit already in another design)

So you're saying the PFC front end won't start operating until the DCDC is active to provide its aux supply? That's odd, I hope you have thought thoroughly about your worst case starting conditions... I agree that with 300V in, a 24:1 ratio for the aux winding is quite marginal...

[Sniper1]

There's a lot to go over there, I'll just start with the turns ratios.
You mention using a center tapped secondary. Therefore with a 6:1 turns ratio, the voltage ratio will actually be 12:1, so with a 400V primary you can't possibly get 48V out.

Even with full wave rectifier on the secondary side, a 6:1 turns ratio does not leave you with much headroom for responding to transient conditions.

Do you have a holdup spec? That can also necessitate more headroom on turns ratio.

Vin 300V+ mostly 380-410vDc 390Vdc nominal ( 300vdc since it will start with that and then powers the APFC stage that gives 390v nominal, the APFC stage works and it was tested a bit already in another design)

So you're saying the PFC front end won't start operating until the DCDC is active to provide its aux supply? That's odd, I hope you have thought thoroughly about your worst case starting conditions... I agree that with 300V in, a 24:1 ratio for the aux winding is quite marginal...

Yes the APFC IC is powered from another later stage in all reference designs , i also added some footrpints for effectively a high voltage LDO to help with start up if things dont go well.
Regarding  how all fits together i attached the datasheet simplified schematic.
Also when i am talking about the secondary as being 6:1 i was referring to 2 of them so yea it also can be called 12:1 if you count turns between the 2 ends that get rectified.
With 6:1 i was thinking it was ok since at nominal i get 390/6 = 65 way way more then nominal 48 with a lot of headroom for loses even if i go for 60V out ( or so i think in my mind).
I am bad at explaining so in a way i am posting a picture since i cant express in words well  this stuff.
Regarding: ``` Do you have a holdup spec? That can also necessitate more headroom on turns ratio.```  more or less 10ms there are is like 660uF capacitance at 390V on the DC buss i calculated that for my APFC stage and should* be enough , then again adding more caps
is way easyer but yea i sort of understand what you mean that at power loss i need to run at lower voltages and still deliver max power.
I sort of forgot about this since i am a bit on the overwhelmed side as of now and would be super happy to get this to run at max power first try.
So yea i am not in the best shape as now.....

[mtwieg]

Also when i am talking about the secondary as being 6:1 i was referring to 2 of them so yea it also can be called 12:1 if you count turns between the 2 ends that get rectified.
With 6:1 i was thinking it was ok since at nominal i get 390/6 = 65 way way more then nominal 48 with a lot of headroom for loses even if i go for 60V out ( or so i think in my mind).
I am bad at explaining so in a way i am posting a picture since i cant express in words well  this stuff.

Here are a few acceptable ways to describe a transformer with 24 primary turns and a center tapped secondary with 8 turns total:
24:8CT
24:4+4
24:4:4 (if the secondary is split into two separate windings on the bobbin).
Describing it as "12:1" or "6:1" is confusing because it doesn't describe the actual turns ratio.

Regarding: ``` Do you have a holdup spec? That can also necessitate more headroom on turns ratio.```  more or less 10ms there are is like 660uF capacitance at 390V on the DC buss i calculated that for my APFC stage and should* be enough , then again adding more caps
is way easyer but yea i sort of understand what you mean that at power loss i need to run at lower voltages and still deliver max power.

If the max output power is ~240W then 660uF at 400V should hold up fine for 10ms.

Do you have a simulation model of the converter? If not, I strongly suggest creating one, it would be very useful for many purposes besides transformer design. Depending on what you want to do, the model does not have to be very detailed. Simulations are usually how I gain confidence in my designs. In many cases simulation is more useful than actual experimentation. Breaking a simulation is much less costly than breaking real hardware.

[Sniper1]

Also when i am talking about the secondary as being 6:1 i was referring to 2 of them so yea it also can be called 12:1 if you count turns between the 2 ends that get rectified.
With 6:1 i was thinking it was ok since at nominal i get 390/6 = 65 way way more then nominal 48 with a lot of headroom for loses even if i go for 60V out ( or so i think in my mind).
I am bad at explaining so in a way i am posting a picture since i cant express in words well  this stuff.

Here are a few acceptable ways to describe a transformer with 24 primary turns and a center tapped secondary with 8 turns total:
24:8CT
24:4+4
24:4:4 (if the secondary is split into two separate windings on the bobbin).
Describing it as "12:1" or "6:1" is confusing because it doesn't describe the actual turns ratio.

Regarding: ``` Do you have a holdup spec? That can also necessitate more headroom on turns ratio.```  more or less 10ms there are is like 660uF capacitance at 390V on the DC buss i calculated that for my APFC stage and should* be enough , then again adding more caps
is way easyer but yea i sort of understand what you mean that at power loss i need to run at lower voltages and still deliver max power.

If the max output power is ~240W then 660uF at 400V should hold up fine for 10ms.

Do you have a simulation model of the converter? If not, I strongly suggest creating one, it would be very useful for many purposes besides transformer design. Depending on what you want to do, the model does not have to be very detailed. Simulations are usually how I gain confidence in my designs. In many cases simulation is more useful than actual experimentation. Breaking a simulation is much less costly than breaking real hardware.

Of so to reiterate:
My transformer is 24:8CT i got the 6/1 ratio from TI calculator and then based on that did math to determine the turns needed for inductance in the primary and then that TXT wall at the beginning and i got 22:8CT or 24:8CT as potential results.
I honestly got so used to N:1 transformer type from uni and all alth in datasheets so i didnt even think abot why i should not simplyfy the fraction, BIG off on me.
Regarding APFC caps yea i expected to be fine since this part was designed with 500W in mind and TI had a capacitor calculator , besides the SMPS that i am making now there is another one that draws power from that same APFC it is a LLC and i cant get it to work .
There is no TI spice model and only an XCEL calculator that i followed , as of now it is not my main priority since TI will release soon a better version of that LLC chip that is also pin compatible so maybe there was something off in it to begin with .
Also that new one may have a SPICE model.

So as of now APFC is way overbuilt and i didnt bother to downscale it since.

Regarding simulation of this design i am trying but failing TI provided Pspice model that i am trying to migrate to LTspice or Qspice
https://www.eevblog.com/forum/projects/help-migrateing-spice-model-from-psipe-to-qspice/new/#new 

It does not error out but still nothing happens , nothing even tries to switch.
Even if it starts to work the data regarding the transformer will be based on the transformer i calculated here, and last time i tried to design a transformer i was waaaay of in terms of inductance ( it was flybacks  well distance inaccuracies may be been a part too but if i remember well it was systematically 1/ or 1/3 of what it was supposed to be so  i heavily suspect a calculation problem on my side). GPT thinks math is correct but it hallucinates on may simpler stuff so it is not that comforting. 

I got primary inductance value from TI calculator so should be ok but man my transformer design scares me since it is planar it is not that easy to adjust later.

[mtwieg]

Regarding simulation of this design i am trying but failing TI provided Pspice model that i am trying to migrate to LTspice or Qspice
https://www.eevblog.com/forum/projects/help-migrateing-spice-model-from-psipe-to-qspice/new/#new 

It does not error out but still nothing happens , nothing even tries to switch.

Oh yeah that was your thread. I did actually get a simple LTspice model working, based on figure 19 of that LM5046 datasheet. See attached. Overall it seems to function, but there are definitely some convergence issues which make the simulation run very slowly, and sometimes stall completely. Not sure if it's in the LM5046 subcircuit, or in the external circuitry.

[Sniper1]

Regarding simulation of this design i am trying but failing TI provided Pspice model that i am trying to migrate to LTspice or Qspice
https://www.eevblog.com/forum/projects/help-migrateing-spice-model-from-psipe-to-qspice/new/#new 

It does not error out but still nothing happens , nothing even tries to switch.

Oh yeah that was your thread. I did actually get a simple LTspice model working, based on figure 19 of that LM5046 datasheet. See attached. Overall it seems to function, but there are definitely some convergence issues which make the simulation run very slowly, and sometimes stall completely. Not sure if it's in the LM5046 subcircuit, or in the external circuitry.

WOW THX
ill play with it this week end,
Inside i didnt see anything that wild maybe it was the Pspice syntax ( not sure yet what u did in there)
Slow is still ok since i can leave a few running in parallel and get progress , i expect it is a few floating nodes that have some odd transient behaviour.

[mtwieg]

I did not change anything inside the lib file. I didn't see any Pspice-specific syntax. But it's possible there is something in there which should change and I missed it (usually I would expect LTspice to emit an error though).

But there's something about the way the model was implemented doesn't play nice with LTspice's solver. The simulation speed frequently dropped from ~10us/s to <100ns/s. I'm betting this depends on subtle factors like the solver settings, and maybe even the version of LTspice being run (I'm running 24.1.9). I also tried using the debugtran option and it reports to stuff inside the LM5046 model as the main challenge with convergence.

[mzzj]

Your flux density and frequency seem rather high on quick glance. Have you checked you core losses and cooling?

[Sniper1]

Your flux density and frequency seem rather high on quick glance. Have you checked you core losses and cooling?

EI set parameters:
Magnetic characteristics (per set)
l/A = 0.33 mm –1
l e = 26.1 mm
Ae = 78.5 mm2
Amin = 77.9 mm2
Ve = 2050 mm 3

Primary Inductance   3.51 mH
Peak Flux Density   0.212 T

And based on the material datasheet that is 3000 kW/m^3
So Core loss = 6.15 W +- something not even sure if that is a lot of not since at max power i will be at like 250W so that is like 2.4%

Then again my Lmag target was 2.5mH and i get 3.5mH  i have some leeway and i could potentially drop my switching frequency to 400-450kHz
Then again i am not even sure if i chose the right curve for my math since 500kHz is that the output inductor will experience but my FETs will switch at half that and IF i look at 250kh in the loses table it is about 1/2 the loses tho i am not surprised about that.
This is very arcane territory for me .
Regarding cooling plann as of now it mostly convection but the enclosure has a 12V fan that is like 10cm diameter so i think it should work ok ish.....
This is also my first high power transformer design so maybe i am forcing or streaking performances here and there. then again i can reduce frequency if need be.
My main problem is that i am not sure what frequency to use when calculating core loses so i went with the worst case.
In a way lets sau i enter the transformer as a sine with 400 Vpk 800 Vpp at 250 kHz, and then after rectification i end up with DC+ ripple at 500 kHz.
Should i use 250 or 500Khz for transformer loses? in a way it is not a sine and the FSFB waveform is sort of  complex but not near as bad as 500KHz.
What would you do in this instance when it comes to math?

https://www.tdk-electronics.tdk.com/download/540200/0fe9e667e8e8afa649f776a2a5a7eb0a/pdf-n95.pdf

[Sniper1]

I did not change anything inside the lib file. I didn't see any Pspice-specific syntax. But it's possible there is something in there which should change and I missed it (usually I would expect LTspice to emit an error though).

But there's something about the way the model was implemented doesn't play nice with LTspice's solver. The simulation speed frequently dropped from ~10us/s to <100ns/s. I'm betting this depends on subtle factors like the solver settings, and maybe even the version of LTspice being run (I'm running 24.1.9). I also tried using the debugtran option and it reports to stuff inside the LM5046 model as the main challenge with convergence.

I tried to run the files u sent but somehow it tries to find a file somewhere in YOUR downloads folder .I ll try a few more things .
And yes it is in the same folder and i uset unarhived the file in a folder.

Also when i tried to convert the model i looked at:

Code: [Select]

*subckt
.MODEL Dnom D IS=100n RS=30m CJO=10p VJ=0.5 EG=0.6
.MODEL S5K VSWITCH RON=1 ROFF=100E6 VON=1V VOFF=0.0V
.MODEL SWCLAMP VSWITCH RON=0.001 ROFF=100E6 VON=10m VOFF=0
.MODEL SdriverT VSWITCH RON=2.7 ROFF=1E6 VON=2.6V VOFF=2.4V
.MODEL SdriverB VSWITCH RON=1E6 ROFF=1.6 VON=2.6V VOFF=2.4V
.MODEL SdriverSRT VSWITCH RON=17 ROFF=1E6 VON=2.6V VOFF=2.4V
.MODEL SdriverSRB VSWITCH RON=1E6 ROFF=5 VON=2.6V VOFF=2.4V
.MODEL NOMNPN NPN RB=350 RC=600 RE=20
.ENDS LM5046
*$
* RSFF
.SUBCKT RSFF5K R S Q NQ
Eff1 PSTATE 0 VALUE { if(V(R)>2.5 & V(S)<=2.5,0,if(V(R)<=2.5 & V(S)>2.5,5,2.5)) }
Rff1 STATE PSTATE 500 
Cff1 STATE 0  9p IC=0
Eff2 PQ 0 VALUE {if(V(STATE)>=4.5,5,if(V(STATE)<=0.5,0,if(V(FFMEM)>2.5,5,0))) }
Rff2 Q PQ  500
Cff2 Q 0  12p IC=0
Eff3 PNQ 0 VALUE {if(V(STATE)>=4.5,0,if(V(STATE)<=0.5,5,if(V(FFMEM)>2.5,0,5))) }
PS useing same LTspice version

[Sniper1]

AND i did some math regarding the heating of the code at 32 C/W amn it will get for fast at 6W even at 3W it can get super hot......
So i am again stuck . Should i try another material and estimate the loses?
Also is my inductance math even ok  to begin with?

[mtwieg]

I tried to run the files u sent but somehow it tries to find a file somewhere in YOUR downloads folder .I ll try a few more things .
And yes it is in the same folder and i uset unarhived the file in a folder.

Hmm that's weird. When I tried to run the files I also saw that there was an absolute path in the netlist... not sure how, since I removed it from the symbol file....

Try the files attached, it solved that problem for me.

AND i did some math regarding the heating of the code at 32 C/W amn it will get for fast at 6W even at 3W it can get super hot......
So i am again stuck . Should i try another material and estimate the loses?
Also is my inductance math even ok  to begin with?

Yeah as mzzj pointed out, a Bpk of 0.2T (Bp-p of 0.4T) is very high for 500kHz. IIRC N95 is more for 100-200kHz range. Something like N49 or 79, or maybe even PC200 or 80, would probably give a decent improvement. But you will still have to reduce Bpk.

[Sniper1]

I tried to run the files u sent but somehow it tries to find a file somewhere in YOUR downloads folder .I ll try a few more things .
And yes it is in the same folder and i uset unarhived the file in a folder.

Hmm that's weird. When I tried to run the files I also saw that there was an absolute path in the netlist... not sure how, since I removed it from the symbol file....

Try the files attached, it solved that problem for me.

AND i did some math regarding the heating of the code at 32 C/W amn it will get for fast at 6W even at 3W it can get super hot......
So i am again stuck . Should i try another material and estimate the loses?
Also is my inductance math even ok  to begin with?

Yeah as mzzj pointed out, a Bpk of 0.2T (Bp-p of 0.4T) is very high for 500kHz. IIRC N95 is more for 100-200kHz range. Something like N49 or 79, or maybe even PC200 or 80, would probably give a decent improvement. But you will still have to reduce Bpk.

This time it runs  like 10us/ s on my CPU, man that is slow but it is running. THX
I think i have a few ides why it runs so slow: Vcc was suposed to be tied to  12-15V but it floats  and there is an LDO inside so probably that acts oddly since technically it should be just for the start and Vcc fluctuates around 7-8V
enough to switch FEts but maybe it is messing with stuff inside since Vcc min is 10V so maybe something inside is not that happy and maybe browning out periodically
Besides that there was the current FB that is implemented with a current source not a shunt/ transformer that might have to do something with it all + the 1 ohm resistor
Anyway now i have something that runs! Again hwo did u even make that run LOL

Regarding the transformer yea maybe not the best material choice, i used this paragraph when picking material:
```For many standard applications up to 100 kHz, materials N27, N41 and N72 can be used. For the
range up to 500 kHz, materials N92, N87, N88, N95, N96 and N97 are suitable. N49 covers the range
from 300 kHz to 1 MHz, PC200 to 4 MHz e.g. for DC/DC (resonance) converters.```

I ll do the math and see what i get with another material ( i dont have that much hope when it comes to reducing switching frequency, or rather not enough ) so new material it is.
Regarding my math for this core i chose , was it at least correct? asking since IF my process is correct then it is just a repeating thing i need to test.
PS based on the thermal C/W i can afford to have loses of about 2W max +- something and some extra cooling

[Sniper1]

added 13V for on the Vcc rail with a diode like the datasheet, may the simulation faster but still averaging like 30us /s
Also the 2 sync rectifier outputs overlap and i dont think it should be like that .....
Then again i didnt check the passive values
Anyway my HDD and CPU can work and i can test stuff  + might also try to also do magnetic simulation to calculate the real flux density

[mtwieg]

This time it runs  like 10us/ s on my CPU, man that is slow but it is running. THX
I think i have a few ides why it runs so slow: Vcc was suposed to be tied to  12-15V but it floats  and there is an LDO inside so probably that acts oddly since technically it should be just for the start and Vcc fluctuates around 7-8V
enough to switch FEts but maybe it is messing with stuff inside since Vcc min is 10V so maybe something inside is not that happy and maybe browning out periodically

Yeah I tried sourcing Vcc with a separate voltage source but didn't notice any improvement.

Besides that there was the current FB that is implemented with a current source not a shunt/ transformer that might have to do something with it all + the 1 ohm resistor

Generally I try and replace things like transformer and optocouplers with dependent sources in order to simplify the simulation. Depends what sort of behavior I'm actually interested in simulating. For example if I want to simulate feedback stability but don't care about realistic power efficiency then I might replace the power semiconductors with voltage-controlled switches or ideal diodes. 

Anyway now i have something that runs! Again hwo did u even make that run LOL

Getting the LM5046 model itself to run (slow and janky) was trivial. Again, just needed to create a symbol and include the .lib file. On the other hand, I spent a couple hours trying to prevent its output from overshooting terrible at startup. Still sucks but probably not a big deal for your purposes.

I ll do the math and see what i get with another material ( i dont have that much hope when it comes to reducing switching frequency, or rather not enough ) so new material it is.

Alternatively, you could increase the number of turns (on all windings) to reduce Bpk. I expect you will need to do this even if you pick an optimal material (unless you also choose a core with a larger Ae).

Regarding my math for this core i chose , was it at least correct? asking since IF my process is correct then it is just a repeating thing i need to test.
PS based on the thermal C/W i can afford to have loses of about 2W max +- something and some extra cooling

I hadn't looked at the core selection math. That's usually a messy optimization, one I don't bother with until other basic things like turn ratios and switching frequency are locked down.

Regarding the SR signals, they look fine to me. Overlap is expected, per the datasheet.

[Sniper1]

This time it runs  like 10us/ s on my CPU, man that is slow but it is running. THX
I think i have a few ides why it runs so slow: Vcc was suposed to be tied to  12-15V but it floats  and there is an LDO inside so probably that acts oddly since technically it should be just for the start and Vcc fluctuates around 7-8V
enough to switch FEts but maybe it is messing with stuff inside since Vcc min is 10V so maybe something inside is not that happy and maybe browning out periodically

Yeah I tried sourcing Vcc with a separate voltage source but didn't notice any improvement.

Besides that there was the current FB that is implemented with a current source not a shunt/ transformer that might have to do something with it all + the 1 ohm resistor

Generally I try and replace things like transformer and optocouplers with dependent sources in order to simplify the simulation. Depends what sort of behavior I'm actually interested in simulating. For example if I want to simulate feedback stability but don't care about realistic power efficiency then I might replace the power semiconductors with voltage-controlled switches or ideal diodes. 

Anyway now i have something that runs! Again hwo did u even make that run LOL

Getting the LM5046 model itself to run (slow and janky) was trivial. Again, just needed to create a symbol and include the .lib file. On the other hand, I spent a couple hours trying to prevent its output from overshooting terrible at startup. Still sucks but probably not a big deal for your purposes.

I ll do the math and see what i get with another material ( i dont have that much hope when it comes to reducing switching frequency, or rather not enough ) so new material it is.

Alternatively, you could increase the number of turns (on all windings) to reduce Bpk. I expect you will need to do this even if you pick an optimal material (unless you also choose a core with a larger Ae).

Regarding my math for this core i chose , was it at least correct? asking since IF my process is correct then it is just a repeating thing i need to test.
PS based on the thermal C/W i can afford to have loses of about 2W max +- something and some extra cooling

I hadn't looked at the core selection math. That's usually a messy optimization, one I don't bother with until other basic things like turn ratios and switching frequency are locked down.

Regarding the SR signals, they look fine to me. Overlap is expected, per the datasheet.

At page 19 in Fig 13 it shows clearly they should be mostly out of phase with each other , or at least mostly .

Anyway regarding the transformer: ill iterate and see what i get
As of now i have 24/4+4 i have inductance to spare so i can try a few other cores in the same shape and or play with lowering the frequency .
Alternatively ill go to 30/5+5 ( not sure how practical this is for planar tho i can see myself putting the aux here easyer.) or 36/ 6+6 ( man that is a lot of turns on the primary)
Well with more turns there will be more inductance to use so lower frequency too so in a way that can help too)

I ll have to make an excell with all the combinations and see what is best at the end...
PS transformer experiences 250kHz not 500kHz so i am at 3W loses so about 100C temp rise so i might be fine with just some small adjustments

I ll write in a few days here my NEW* optimised transformer.

Regarding current sensing i was thinking of a shunt like on the low side on the H bridge. ( might not the best in practice but simple for SPICE).

Regarding simulation speed: i think it may have to do something with how GND is tied , there is no GND pin and inside 0 is the real GND note, ill try to  make a very modified copy with 0 node renamed to GND and an extra pin.
Actualy now i remember that i did that change in th einitial posted file, ill try to then add GND to the symbol u made and see how it goes

[mtwieg]

At page 19 in Fig 13 it shows clearly they should be mostly out of phase with each other , or at least mostly .

Right, out of phase, but they also overlap. In the LTspice sim, I see that once the circuit reaches steady state (SS and SSSR both have finished charging), all the waveforms match up exactly with figure 13.

However, if you look at the SR waveforms while SSSR is still charging, they look like figure 14a. I'm not sure why the chip operates like this, but the model seems to agree with the datasheet.

Anyway regarding the transformer: ill iterate and see what i get
As of now i have 24/4+4 i have inductance to spare so i can try a few other cores in the same shape and or play with lowering the frequency .

Lowering the switching frequency (while making no other changes) will increase core losses, not decrease them.

Have you attempted to estimate winding losses? Not sure how one would approach this for planar transformers. Most nomographs of winding loss and Rac will be derived from round wire or foil wound on bobbins, and won't apply to PCB traces on a planar transformer...

I ll have to make an excell with all the combinations and see what is best at the end...

Yes, spreadsheets are good.

PS transformer experiences 250kHz not 500kHz so i am at 3W loses so about 100C temp rise so i might be fine with just some small adjustments

Oh duh, had the transformer confused with the filter choke. So yeah N95 might be fine.

Regarding simulation speed: i think it may have to do something with how GND is tied , there is no GND pin and inside 0 is the real GND note, ill try to  make a very modified copy with 0 node renamed to GND and an extra pin.

I really doubt that will help. It's pretty normal for subcircuits to use the global 0 net everywhere. It's only an issue if you need to reference the model to another net (which will make things much more complicated and slow).

I did find one major improvement: if you change the definition of SWCLAMP to have RON=0.1 instead of R=0.001, this makes things run much more smoothly, and AFAIK has no significant impact on simulation results. Still not super fast, but it doesn't get snagged at random points.

[Sniper1]

At page 19 in Fig 13 it shows clearly they should be mostly out of phase with each other , or at least mostly .

Right, out of phase, but they also overlap. In the LTspice sim, I see that once the circuit reaches steady state (SS and SSSR both have finished charging), all the waveforms match up exactly with figure 13.

However, if you look at the SR waveforms while SSSR is still charging, they look like figure 14a. I'm not sure why the chip operates like this, but the model seems to agree with the datasheet.

Anyway regarding the transformer: ill iterate and see what i get
As of now i have 24/4+4 i have inductance to spare so i can try a few other cores in the same shape and or play with lowering the frequency .

Lowering the switching frequency (while making no other changes) will increase core losses, not decrease them.

Have you attempted to estimate winding losses? Not sure how one would approach this for planar transformers. Most nomographs of winding loss and Rac will be derived from round wire or foil wound on bobbins, and won't apply to PCB traces on a planar transformer...

I ll have to make an excell with all the combinations and see what is best at the end...

Yes, spreadsheets are good.

PS transformer experiences 250kHz not 500kHz so i am at 3W loses so about 100C temp rise so i might be fine with just some small adjustments

Oh duh, had the transformer confused with the filter choke. So yeah N95 might be fine.

Regarding simulation speed: i think it may have to do something with how GND is tied , there is no GND pin and inside 0 is the real GND note, ill try to  make a very modified copy with 0 node renamed to GND and an extra pin.

I really doubt that will help. It's pretty normal for subcircuits to use the global 0 net everywhere. It's only an issue if you need to reference the model to another net (which will make things much more complicated and slow).

I did find one major improvement: if you change the definition of SWCLAMP to have RON=0.1 instead of R=0.001, this makes things run much more smoothly, and AFAIK has no significant impact on simulation results. Still not super fast, but it doesn't get snagged at random points.

Here is the spread sheet :
( also ateched fo easyer reference since man formating went bad here)
core   material   Ve [mm^3]   loses [kW/m^3]   turns   Primary inductance [mH]   Flux density [mT]   Loses [w]   Delta temp C
ELP 22/6/16    N95    2050   1500   24:4   3,5   0,21   3,075   101,475
ELP 22/6/16    N95    2050   600   30:5   5,5   0,17   1,23   40,59
ELP 22/6/16    N95    2050   500   36:6   7,9   0,14   1,025   33,825
ELP 22/6/16    N97   2050   1600   24:4   3,5   0,21   3,28   108,24
ELP 22/6/16    N97   2050   1000   30:5   4,7   0,17   2,05   67,65
ELP 22/6/16    N97   2050   700   36:6   6,8   0,14   1,435   47,355

TLDR N95 seems the best but i need to add an extra turn on the secondary, tho 40 C temp rise is not the best it is safe since i will have a fan anyway and ambient is sort of cool anyway .

so 30:5+5 seems to be the winner , as for the secondaries i was wandering if i should use 1 or 2 now it is heavy bias on 2 since i would get 48/5*2 so about 19V - loses and diode rectification i should be ok , if need be even add LDO or zener regulator to drop it to safe gate voltages , also alternative is 9.5v so a bit low for gate drives but enough it need be , maybe ill use a resistor to add or remove a turn...

Also i need these bias windings for both sides .
What do you think should i continue with 30:5+5 ?

[mtwieg]

Here is the spread sheet :
( also ateched fo easyer reference since man formating went bad here)
core   material   Ve [mm^3]   loses [kW/m^3]   turns   Primary inductance [mH]   Flux density [mT]   Loses [w]   Delta temp C
ELP 22/6/16    N95    2050   1500   24:4   3,5   0,21   3,075   101,475
ELP 22/6/16    N95    2050   600   30:5   5,5   0,17   1,23   40,59
ELP 22/6/16    N95    2050   500   36:6   7,9   0,14   1,025   33,825
ELP 22/6/16    N97   2050   1600   24:4   3,5   0,21   3,28   108,24
ELP 22/6/16    N97   2050   1000   30:5   4,7   0,17   2,05   67,65
ELP 22/6/16    N97   2050   700   36:6   6,8   0,14   1,435   47,355

Here's what I get for just the first row:
1. For Bpk and core losses, need to first establish the volt-time product. For Vin=400V, Vout=48V, Np/Ns=6, and fsw=250kHz, I get vt=5.76e-4 v*s. Ae=78.5  mm^3. So for Np=24, I calculate Bpp = 0.307 T and Bpk=0.153T.
2. Even assuming your Bpk=0.21T is correct, the Pv at 250kHz should be more like >2000 kW/m3 (actually need to extrapolate the N95 datasheet curves in frequency a bit). At Bpk=0.153T, probably more like 1100 kW/m3.
3. For Pv=1100 kW/m3, total Pc would be 2.26W.
4. Datasheet doesn't provide a way to estimate temperature rise, but suggests a maximum Pc of 1.25W at 25C ambient.

For the second row I get Bpk=0.123T, Pv=600 kW/m3, and Pc=1.23W. More in line with the datasheet's suggestion.

[Sniper1]

Here is the spread sheet :
( also ateched fo easyer reference since man formating went bad here)
core   material   Ve [mm^3]   loses [kW/m^3]   turns   Primary inductance [mH]   Flux density [mT]   Loses [w]   Delta temp C
ELP 22/6/16    N95    2050   1500   24:4   3,5   0,21   3,075   101,475
ELP 22/6/16    N95    2050   600   30:5   5,5   0,17   1,23   40,59
ELP 22/6/16    N95    2050   500   36:6   7,9   0,14   1,025   33,825
ELP 22/6/16    N97   2050   1600   24:4   3,5   0,21   3,28   108,24
ELP 22/6/16    N97   2050   1000   30:5   4,7   0,17   2,05   67,65
ELP 22/6/16    N97   2050   700   36:6   6,8   0,14   1,435   47,355

Here's what I get for just the first row:
1. For Bpk and core losses, need to first establish the volt-time product. For Vin=400V, Vout=48V, Np/Ns=6, and fsw=250kHz, I get vt=5.76e-4 v*s. Ae=78.5  mm^3. So for Np=24, I calculate Bpp = 0.307 T and Bpk=0.153T.
2. Even assuming your Bpk=0.21T is correct, the Pv at 250kHz should be more like >2000 kW/m3 (actually need to extrapolate the N95 datasheet curves in frequency a bit). At Bpk=0.153T, probably more like 1100 kW/m3.
3. For Pv=1100 kW/m3, total Pc would be 2.26W.
4. Datasheet doesn't provide a way to estimate temperature rise, but suggests a maximum Pc of 1.25W at 25C ambient.

For the second row I get Bpk=0.123T, Pv=600 kW/m3, and Pc=1.23W. More in line with the datasheet's suggestion.

I found some data regarding thermal resistance and cores here: https://www.e-magnetica.pl/doku.php/thermal_resistance_of_ferrite_cores

... as for cooling i will have a fan so i have some more margin

So you say row 2 is a reasonable transformer design ? or at least something that will work decently most of the time?
If yes then i can try and use that for simulations and see how stuff goes from there . i effectively have 2 1.6mm PCB for windings so ill think how to spread the turns and see how it goes , JLC seems not to change price if i go for 1mm so 3 1mm PCB are also on the table tho this way will be way harder to assemble and properly design .

[mtwieg]

So you say row 2 is a reasonable transformer design ? or at least something that will work decently most of the time?

At this point one would normally also estimate winding losses and check that they are similar to core losses before moving forward. However for planar designs it seems that there isn't a wealth of nomographs available that one can use to estimate/optimize winding losses... so you may have to make your best guess on winding design and measure it experimentally.

I personally would go for a 24:5+5 or 30:6+6, to allow for better handling of line dips and/or load transients. Also will reduce core losses a bit more.

Also if this is for a real product I would strongly look into safety/certification aspects before going too much further (I'm guessing this transformer is going to comprise the protective insulation in a AC-DC power supply, meaning this will be necessary). One does not often see planar transformers used as protective insulation, and I'm not familiar with what tricks designer pull off to meet safety standards with planar designs. But it may throw a wrench in your plans at some point...

[Sniper1]

So you say row 2 is a reasonable transformer design ? or at least something that will work decently most of the time?

At this point one would normally also estimate winding losses and check that they are similar to core losses before moving forward. However for planar designs it seems that there isn't a wealth of nomographs available that one can use to estimate/optimize winding losses... so you may have to make your best guess on winding design and measure it experimentally.

I personally would go for a 24:5+5 or 30:6+6, to allow for better handling of line dips and/or load transients. Also will reduce core losses a bit more.

Also if this is for a real product I would strongly look into safety/certification aspects before going too much further (I'm guessing this transformer is going to comprise the protective insulation in a AC-DC power supply, meaning this will be necessary). One does not often see planar transformers used as protective insulation, and I'm not familiar with what tricks designer pull off to meet safety standards with planar designs. But it may throw a wrench in your plans at some point...

Why 24:5+5? and 30:6+6? my turns ratio would ideally be 6n:n +n and what you propose it like 5n:n+n i dont understand the logic.
Can you please explain why i should go for 5n:n+n and not 6n:n+n? what is your train of thought? Regarding winding loses, well it depndsTM i need to design and then use estimate ESR and parasitic to estimate loses

Regarding safety yea and now, i did study some high voltage safety requirements but not for AC-DC specifically. I saw some planar transformer in some GaN USB chargers so why not ?
And yea this revision is mostly for learning since i never designed something this powerful before yet alone transformers but it it works it could be a good starting point. As for personal safety yea i am taking care of that.

As of now the most concearning part for me is the inductance value for the primary since there i messed up big time last time. Since it is PSFB leakage inductance is not a problem it is actually good up to some point.

[mtwieg]

Why 24:5+5? and 30:6+6? my turns ratio would ideally be 6n:n +n and what you propose it like 5n:n+n i dont understand the logic.
Can you please explain why i should go for 5n:n+n and not 6n:n+n? what is your train of thought? Regarding winding loses, well it depndsTM i need to design and then use estimate ESR and parasitic to estimate loses

For your nominal conditions (Vin=400V, Vout=48V), that means your duty cycle would be 0.72 (referring to the secondary side). But you mentioned also wanting Vout up to 60V. And realistically you should be capable of operating at just 90% of your nominal Vin (to meet holdup time). So that would mean at worst case your duty cycle would be exactly 1.00. No headroom for handling load transients at all. Also if you plan on using a current transformer for sensing bridge current, you need to reserve some duty cycle for CT reset. And I assume you intend to use peak current mode control, in which case you want to avoid operating near 100% to make transient response faster. Using a 5:1+1 turn ratio should allow more headroom for such things.

Regarding safety yea and now, i did study some high voltage safety requirements but not for AC-DC specifically. I saw some planar transformer in some GaN USB chargers so why not ?

Sure it's definitely possible, but depending on what level of insulation you need (basic, reinforced, etc), you may need to drastically change the implementation of the windings.

As of now the most concearning part for me is the inductance value for the primary since there i messed up big time last time. Since it is PSFB leakage inductance is not a problem it is actually good up to some point.

True, PSFB is tolerant of more leakage inductance. Magnetizing inductance is important for maintaining soft switching under light load conditions though. In the worst case, if you Lmag is too high then you can put a large inductance in parallel with the primary to help.

[Sniper1]

Why 24:5+5? and 30:6+6? my turns ratio would ideally be 6n:n +n and what you propose it like 5n:n+n i dont understand the logic.
Can you please explain why i should go for 5n:n+n and not 6n:n+n? what is your train of thought? Regarding winding loses, well it depndsTM i need to design and then use estimate ESR and parasitic to estimate loses

For your nominal conditions (Vin=400V, Vout=48V), that means your duty cycle would be 0.72 (referring to the secondary side). But you mentioned also wanting Vout up to 60V. And realistically you should be capable of operating at just 90% of your nominal Vin (to meet holdup time). So that would mean at worst case your duty cycle would be exactly 1.00. No headroom for handling load transients at all. Also if you plan on using a current transformer for sensing bridge current, you need to reserve some duty cycle for CT reset. And I assume you intend to use peak current mode control, in which case you want to avoid operating near 100% to make transient response faster. Using a 5:1+1 turn ratio should allow more headroom for such things.

Regarding safety yea and now, i did study some high voltage safety requirements but not for AC-DC specifically. I saw some planar transformer in some GaN USB chargers so why not ?

Sure it's definitely possible, but depending on what level of insulation you need (basic, reinforced, etc), you may need to drastically change the implementation of the windings.

As of now the most concearning part for me is the inductance value for the primary since there i messed up big time last time. Since it is PSFB leakage inductance is not a problem it is actually good up to some point.

True, PSFB is tolerant of more leakage inductance. Magnetizing inductance is important for maintaining soft switching under light load conditions though. In the worst case, if you Lmag is too high then you can put a large inductance in parallel with the primary to help.

Yea i totally forgot about 60V since i got scared of the core loses and went on a long optimisation path. In a way 5:1+1 mean less turn on the primary so easyer to design.
As for isolation my aim if basic (1500V)  but if i get it to be reinforced ( 3kv) then great , since for now this is a 1 off i have a few ways to make it better, with Kapton.
Anyway now alas i can take this transformer and resign the other parts, and i hope that untill the end of the mounth i can finish all the design work and order a PCB.

THX for the help
I am still a bit afraid of primary inductance but that may be just my PTSD from the past.
Ill post updates here as work progresses.