By redrawing the symbol and re-arranging ..., it becomes much clearer. The bottom two gates (U31B & D) are simply an RS latch. The only difference is that the "prohibited condition" for a normal RS latch is not a problem here because there is no complement of it as another output (so no logical problem). I've included the truth table on the LHS of it.
So signals from 4 sources come in and become the 4-bit preset number (c0) of the counter (counting up), which, once preset, will count up until it's full (reaching 16, i.e. after 16-c0 clock pulses), when carry-out will be set (and all the bits reset). Since there is a bar on the top of C_OUT, which I think means it's the invert of C_OUT, so at that moment C_OUT' (I'm using "'" for a bar) will become L.
The way the magic initial count c0 is set is really difficult to decipher. Just to make this a little closer, I've figured out at least what the input bits are. For this I need to start from the genesis of the clock signal.
It starts from a square wave generator comprising a UJT, the frequency of which can be adjusted at run time through human interface (pedal action). This pulse signal, along with an ENABLE signal (as I understand it), feeds into a 4040 12-bit counter --- only 7 bits are used as a series of pulse signals for output. The lowest bit Q0 has 1/2 of the frequency of the (enabled) input signal (because it flips, from L to H or H to L, once in one cycle of the input). Next one Q1 has 1/2 of the frequency of Q0, and so on, until Q6 (the 7th bit).
These 7 pulses signals go through a series of gates (AND, OR, etc.). When reaching the 4 input ports (bits) of 4516, I've figured out the formulas for all of them (noted on the top). I've also visualised these series of signals and the result of the formulas, as well as the value of the 4-bit number, in Excel. So you can get an idea of --- suppose RESET is L, i.e. at the moment of presetting the initial count --- the likelihood of c0 being non-zero (highlighted in green) and its value (be it zero or not). (Also shown is the result of c0 for another 4516, 2-3C.)
Whichever of these c0 values is set (when the CLOCK signal is H), it will count up upon every clock pulse, and --- as soon as the count reads 16 sends out a carry-out signal (inverted) --- unless RESET becomes H, at which point it will start over again.
(After this 4040, the Q1 signal feeds into the LCK pin of other logic chips, so I'm now naming it "CLOCK".)
While this seems closer, it is still a huge maze to navigate.