AD9854 Synchronization

[ezalys]

Analog devices has an application note on synchronizing a pair of AD9851s/AD9854s: https://www.analog.com/media/en/technical-documentation/application-notes/an-605.pdf. That variable delay block is tripping me up a bit, though, especially because the timing is so incredibly tight. Has anyone tried to implement this? I was thinking of soldering down a handful of buffers with shorting 0 ohm resistors to try and tune the delay with gates, but I don't think this gives the needed granularity. There's also the prospect of using delay lines but 500 ps is still a bit too long for delay lines. Anyone have any suggestions?

[radar_macgyver]

Use a clock distribution chip (like an HMC7043 or HMC7044), each clock output has a programmable delay block that can be used to compensate for PCB trace length differences. The sync outputs can be used for the I/O update signals. I had done this once with AD9857sAD9517-3s feeding two AD9854s (fclk 160 MHz) and used length matching on the IO update and clock traces, and didn't really need any further matching using the programmable delays.

edit: fixed the clock dist part

[Bud]

A trick i once used was instead of the variable delay  I used a clock buffer gate powered from a variable power supply. By changing the supply voltage by tiny amount the clock gate propagation delay changed, effectively playing a role of the delay element equivalent in AN-605. That way i sync-ed two AD9912 chips clocked at 1 GHz.

[nctnico]

Analog devices has an application note on synchronizing a pair of AD9851s/AD9854s: https://www.analog.com/media/en/technical-documentation/application-notes/an-605.pdf. That variable delay block is tripping me up a bit, though, especially because the timing is so incredibly tight. Has anyone tried to implement this? I was thinking of soldering down a handful of buffers with shorting 0 ohm resistors to try and tune the delay with gates, but I don't think this gives the needed granularity. There's also the prospect of using delay lines but 500 ps is still a bit too long for delay lines. Anyone have any suggestions?

It doesn't look like a variable delay to me but a fixed delay that must be determined at the design time. Something that is easely achieveable by varying the PCB trace lengths. Rule of thumb is about 6ps of delay per mm. If you draw a timing diagram for the entire system including minimum and maximum delays, than you should be able to determine how much delay you need to make sure the timing constraints around the synchronisation are met.

[Bud]

You can't do it this way reliably because of the D-Flop part timing manufacturing tolerances. Even high speed logic parts may have propagation delays variances in nanosecond range.

[nctnico]

You can't do it this way reliably because of the D-Flop part timing manufacturing tolerances. Even high speed logic parts may have propagation delays variances in nanosecond range.

A small FPGA / CPLD or PECL part should be able to do the trick though. Likely there are more specialised parts as well. Like the PO74G74A  from Potato Semiconductor.

[Marsupilami]

Use a clock distribution chip (like an HMC7043 or HMC7044),

 ↑ THAT  ↑

Although in this case I probably would use something simpler like the AD9513.
Output 0 and 1 with divider=1 routed as length matched diff pairs to the REFCLKs, while OUTPUT 2 in CMOS mode with a high divider sent to the I/O Update Clock inputs.
The beauty of it is then he SYNCB pin can be used to gate Output 2 to generate the sync pulse for the DDS. Output 0 and 1 is unaffected if the divider is 1. Moreover Output 2 has an adjustable delay that can be tuned to get the sync pulse right.

[ezalys]

I like that idea but it seems to me that OUT2 and OUT2B are compliments. I'll definitely look into doing something like this -- thank you!

[Marsupilami]

I like that idea but it seems to me that OUT2 and OUT2B are compliments. I'll definitely look into doing something like this -- thank you!

My bad, I misread that sentence while skimming through the datasheet. (In retrospect it was dumb considering the driver electronics.) Anyway... AD9508? I haven't looked into it a lot, but you get the concept, there are lot of options.

[ezalys]

Yeah! All helpful suggestions. Thank you everyone who commented!

[nctnico]

Still I feel using a clock distribution chip is an over-complicated solution. You'll need to calibrate every circuit which is not very nice if it is to be produced in larger numbers. A solution which meets the timing 'by design' is much more simple to build.

[ezalys]

It would be great if there was a "by design" way to do this but I can't imagine finding buffers and flipflops that meet timing closure with their tolerances. Not even the potato parts claim to.

For what it's worth, my initial approach was just to stack buffers but I can't find one with much less than 1 ns. There's a 1.8 ns window I need to hit -- so I would prefer maybe 20% of that or 400 ps per buffer.

[nctnico]

Did you look at PECL devices? You will need to change the termination resistors to get to TTL compliant voltages levels but I think this is doable.

Another option is to use an FPGA (from Gowin for example) to implement a multi-channel DDS ( https://www.fpga4fun.com/DDS.html ). Synchronisation between channels is trivial in that case and not some kind of afterthought as it seems to be the case with the AD9854 device. Using an FPGA might also be a more cost effective solution.

[radar_macgyver]

If you're not tied to using the 9854, use a newer DDS chip that has explicit synchronization mechanisms (9910), or one of the multichannel DDS parts.

[Bud]

They still require tight setup time so you end up with same problem.

[radar_macgyver]

The AD9910 and AD9957 provide a programmable delay on SYNC_IN to compensate for board layout differences and process/temperature variations. It even includes a validation block which will flag cases where setup/hold was not met - can't get simpler than that when synchronizing devices with GHz+ clocks.