Custom FPGA+SoC SDR Transceiver: H7113R with Two Coherent RF/DDC Rx Channel

[Xdx]

Hi everyone,

I wanted to share a deep-tech SDR project I’ve designed and fully implemented. It’s a custom, standalone FPGA + ARM SoC-based HF + 50 MHz SDR transceiver called the XtremeDx H7113R.

My goal was to build a high-performance direct conversion SDR system.

Key Architecture & Hardware Specs:

Receiver Architecture: Two coherent RF and DDC channels utilizing a hardware-level phasing-add matrix implemented directly inside the FPGA.

Processing: Dual-core ARM Cortex-A7 (1.2 GHz) dedicated to GUI handling and high-level DSP, paired with a custom FPGA fabric.

RF Conversion: 2x 16-bit LTC2208 ADC (122.88 MSPS) and 14-bit TxDAC utilizing full LVDS interfaces.

FPGA-Based Phasing-ADD Mode: A fully hardware-implemented, real-time, running inside the FPGA fabric. It processes the two coherent RX channels, allowing completely independent phase rotation and magnitude scaling per channel.

Interference Mitigation: CNLMS-based I/Q adaptive noise canceling (tested and validated using the same signal on RF inputs).

RF Routing: Two completely independent RX RF routing blocks, each integrating a switchable 20 dB preamplifier, 0.5 dB step attenuator, HPF, and direct ADC access via rear SMA connectors for subsampling/custom front-ends.

Power Amplifier: Delivers 120–140W PEP with 36–38 dB PEP IMD3 linearity across HF + 50 MHz bands.

Audio DSP: Separate 8-band EQ for both Rx and Tx AF signals.

Connectivity: High-bandwidth USB 3.0 (FT601) interface for direct FPGA-to-PC streaming (32-bit Sync FIFO implemented in VHDL) + USB 2.0 for ARM-to-PC communication.

Display: 7" TFT panel running a custom UI with a 70 fps refresh rate. It features 2D/3D spectrum views and a dedicated Polar Plot for the Phasing-ADD and ANC modes, visualizing the real-time magnitude and phase rotation per channel.

RF Routing and Linearity Performance: By routing the LTC2208 RF ADC without a preamplifier through the RF router, the system yields its maximum dynamic range and IIP3. Additionally, the 20 dB preamplifier maintains high IIP3 and OIP3 performance. With the internal PGA set to 0, the LTC2208 achieves a theoretical IIP3 of +48 dBm in this specific design.

Receiver Sensitivity (MDS Performance):

CW (100 Hz filter, NR ON): Highly discernible down to -136 dBm (Estimated nominal MDS: -133 to -136 dBm)

SSB (2.7 kHz filter, NR ON): Distinctly audible down to -126 dBm (Estimated nominal MDS: -123 to -125 dBm)

The Transceiver is fully assembled and functional.

Some details.

https://uprog.blogspot.com/2026/08/xtremedx-h7113r-transceiver.html

[ftg]

Very impressive project.
What mosfets did you end up using the the RF power amplifier?

The google drive links for the RFDSP and Power supply schematics require requesting access.
If the project gets more popular, the requests might get tedious.

[Xdx]

Thanks.

"What mosfets did you end up using the the RF power amplifier?" MRF101.
"The google drive links for the RFDSP and Power supply schematics require requesting access." Yes.

Regards,
Xdx

[Weston]

Super cool! Have you considered trying digital pre-distortion? With this setup you should be able to cancel the harmonics of your carrier in addition to the intermodulation products. This would theoretically allow you to replace your output filter bank with only a fixed low-pass filter. Very few systems have the hardware capability to do that and yours is one of them.

[Xdx]

Hi.
Thanks.
Yes, I'm quite familiar with the details of that, and the hardware has the resources for it. I'm actually planning to implement it sometime in the future.

Regards,
Xdx

[LeslieGuo]

For two coherent RX channels, the RF side is usually the easy half — getting the two digital streams to have a known, repeatable phase relationship is where builds quietly fail. A few things that matter in practice:

1. Share everything that defines phase. Both channels need a common LO (or LOs phase-locked to one reference) and a common sampling clock. Two independent synthesizers will give you a relative phase that drifts with temperature, which looks like "the hardware is broken."

2. Align the digital start point. Even with identical clocks, the two DDCs can come out of reset on different samples, so the channels have an arbitrary fixed offset. Assert the converter/D DC sync together and use the device's multi-tile/synchronization sequence so latency is deterministic power-up to power-up. Reset alignment is the step most people miss and then chase in software.

3. Measure residual error honestly. Feed both inputs from one source through a calibrated splitter, with matched trace lengths and identical gain/filter settings, and capture the relative phase over time and temperature. Subtract the measured static offset in the FPGA; what remains tells you whether your coherence is limited by clock phase noise, path mismatch, or thermal drift.

4. Budget for analog mismatch. Below a few hundred MHz even small length differences are cheap, but at the top of the range matching gets unforgiving — equal connectors, cable lengths and balun/front-end parts, or calibrate it out.

One question on the design: is the coherence target a fixed static offset you can calibrate once, or do you need to track phase continuously while operating? That decides whether a startup calibration is enough or you need a continuous reference/correction path.

[Xdx]

The coherence target in our design is a fixed, static offset, so a startup calibration is sufficient.
In fact, in certain modes, the system works perfectly even without any specific calibration.
Our hardware and digital architecture ensures this stability through the following choices:Common Clock:

Both ADCs share the exact same clock source, driven by a single oscillator.Deterministic Sampling and Capture:
The DDC captures the samples from both ADCs synchronously, using the output clock of one of the ADCs (either one can be used).
To guarantee this, we implemented strict bus and clock length matching on the PCB.Flexible Digital Processing:
We run two identical DDCs in the FPGA, featuring configurable phase offset and magnitude scaling.Regarding the analog path:

The preamplifier inside the RF router may introduce a minor phase and magnitude delta between the two RF channels when enabled.
However, since the signal magnitude across the two antennas (or antenna elements) is relative anyway, this delta is practically negligible.
More importantly, the user can manually adjust the relative phase and magnitude values in real time (aided by a polar plot visualization) when operating in phase-add mode.
Consequently, since our architecture inherently minimizes cross-channel asynchronicity, the system works perfectly in standard phase-add mode from two antennas, even without any special calibration.
If maximum accuracy is required, compensating for the static offsets just once at startup is more than enough.