RoGeorge- my only question is why? Graf and Sheets used to publish a lot innovative stuff in Radio-Electronics magazine in the US. I would look at their stuff and analyze their circuits and generally found them to be highly "optimized". They couldn't be changed much and preserve their function. What's wrong with the 2N3904 as the output stage. Its operating class C. What is your goal in this?
The goal is tinkering with radio. For the fun of it, and because I have close to zero hands-on experience with RF. Never matched an antenna, let alone designing a matching network. In the last couple of days I have read a few chapters from the "RF Circuit Design" by Chris Bowick, and it is much clear now how to deal with matching networks.
(Side note, during this read I have realized how I can just raise the max voltage output of my AWG
without a step up transformer, by simply tuning its 50\$\Omega\$ output to a much bigger, say 5k\$\Omega\$, load - that would give enough voltage swing to curve trace any Zener

)
As for the why not a 2N3904, that's just me being silly. I have found in the scrap boxes two TTL oscillator-cans on 4.9152MHz, from the 80's or so. Hooked the PSU alligators to the GND/+5V pins, and the oscillators were working fine.
Wanted to use them for something, anything. 4.9152MHz may seem a strange frequency, it's a multiple of 2
n for RS232 baud rates. Not interested to do any TTL RS232 project, but when divided by 6, the frequency matches one of the AM MW channels, 819kHz. Here the MW broadcast band is mostly empty, has only 2 radio stations left, and not sure for how long (other EU states already discontinued their AM broadcasts, it is all FM or digital nowadays).
So, I thought I might make an AM modulator (for listening to audio books at the countryside) using "TTL ICs only", that's why trying to use a 74N06 instead of a BJT.

Meanwhile, the more I read from "RF Circuit Design" by Chris Bowick, the less it makes sense to stick to that "TTL only" ad-hoc design goal. I'll probably just use a discrete NPN instead of the open collector of a logic gate.