Please, advice cheap DDS up to 200MHz

[Nova_PA]

Hello!
For amateur construction I need really cheap, avialable on AliExpress frequence sinthesizer.
The thing like SI5351 should be ideal, but I need about 180-200MHz maximal frequence.

Please, advice.

[CaptDon]

The TinySA Ultra can do signal generation. Not sure if it will be what you need. Check the specs.

[radiolistener]

Most of si5351 instances working ok up to 200 MHz.

According to datasheet, si5351 can produce frequency from 2.5 kHz to 200 MHz.




But be careful, there was 150 MHz limit in first edition of si5351 datasheet.
So it's possible, that some very old si5351 instances from first production series may not work stable above 150 MHz.

If you want frequencies above 200 MHz, there is ADF4351, it can produce frequency from 35 MHz to 4400 MHz

[gf]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

[radiolistener]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

I suspect that there is no DDS which can generate 200 MHz sine 

You can easily get 200 MHz sine by adding simple low pass filter with cut-off at about 250 MHz on si5351 output

[gf]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

I suspect that there is no DDS which can generate 200 MHz sine 

For example, SDG6022X can create 200 MHz,  SDG7102A can even create 1 GHz. They are not exactly cheap, though.
I have also seen AD9959 boards (500MSa/s, should also work up to 200 MHz) on eBay, but also with a 3-digit price tag.
OP should answer if he really needs a DDS, as specified in the subject. Maybe he does not.

[radiolistener]

For example, SDG6022X can create 200 MHz,  SDG7102A can even create 1 GHz. They are not exactly cheap, though.

it uses discrete high speed DAC with FPGA

I have also seen AD9959 boards (500MSa/s, should also work up to 200 MHz) on eBay, but also with a 3-digit price tag.

it seems that it can, but I'm sure si5351+LPF will produce much more clean sine... 

[coromonadalix]

check some dds boards on Ebay, you'll get some ideas

real  dds chips     not the junk chineesiums with pseudo fpga's cpld's   blah blah

[Bud]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

I suspect that there is no DDS which can generate 200 MHz sine 

You can easily get 200 MHz sine by adding simple low pass filter with cut-off at about 250 MHz on si5351 output

And if you retune it to 50 MHz you will have to add a 60MHz lowpass filter. And if you retune to 10 MHz you will have to add a 15MHz lowpass filter. Therefore, you have to have a bunch of switchable lowpass filters and activate them based on what sinewave frequency you need to output.
With a DDS you only need one lowpass filter with the cut-off at 0.4...0.45  clock frequency of the DDS.

[Bud]

I suspect that there is no DDS which can generate 200 MHz sine 

None of a DDS generates sine. With addition of a lowpass filter AD9912 or AD9957 can output up to 450MHz sine (with -50dBc spurs worst case depending on output frequency)

[Bud]

Read my post below before buying a DDS board from Ali or eBay

https://www.eevblog.com/forum/rf-microwave/all-you-need-to-know-about-the-chinese-ad9959-ebay-board

[iMo]

I suspect that there is no DDS which can generate 200 MHz sine 

None of a DDS generates sine. With addition of a lowpass filter AD9912 or AD9957 can output up to 450MHz sine (with -50dBc spurs worst case depending on output frequency)

Afaik, ADI's DDSes are producing "sine". There are 10bits/14bits DACs inside with sine lookup tables (sure, you need the low pass as well)..

[langwadt]

I suspect that there is no DDS which can generate 200 MHz sine 

None of a DDS generates sine. With addition of a lowpass filter AD9912 or AD9957 can output up to 450MHz sine (with -50dBc spurs worst case depending on output frequency)

they both output sine, that why they have a DAC

[MasterT]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

I suspect that there is no DDS which can generate 200 MHz sine 

You can easily get 200 MHz sine by adding simple low pass filter with cut-off at about 250 MHz on si5351 output

And if you retune it to 50 MHz you will have to add a 60MHz lowpass filter. And if you retune to 10 MHz you will have to add a 15MHz lowpass filter. Therefore, you have to have a bunch of switchable lowpass filters and activate them based on what sinewave frequency you need to output.
With a DDS you only need one lowpass filter with the cut-off at 0.4...0.45  clock frequency of the DDS.

  Having multiple filters offers one serious advantage, it lowers THD+noise level down to unprecendented level, depends on order of the filters, of course,   5-9-th  would get -100 dBc.  There is no DDS capable to produce same qualilty sinewave, and OPA buffer is another story. Filters solved both problems at once - DDS limitation & OPA's.

 Recently I was considering to buy cheap 50-60-100 MHz DDS generator, but after watching some video on ytube devoted quallity of the signal, I dicided not to. 

Cost is another advantage.   This makes me wander, why those guys stubbornly follow FPGA + DAC route, instead of $1 PLL + bunch of LC filters for a penny ?

[MarkT]

I suspect that there is no DDS which can generate 200 MHz sine 

There certainly are...  Analog Devices have a large number of them. AD9915 clocks at 2.5GHz for instance, or the very powerful AD9174, 12.6GHz clock and 16 bit resolution (don't check the price if you are easily shocked!)

[langwadt]

SI5351 is not a DDS generator. It is a PLL-based clock generator and generates only square wave signals with ~1ns rise time. It cannot generate sine wave or arbitrary waveforms.

I suspect that there is no DDS which can generate 200 MHz sine 

You can easily get 200 MHz sine by adding simple low pass filter with cut-off at about 250 MHz on si5351 output

And if you retune it to 50 MHz you will have to add a 60MHz lowpass filter. And if you retune to 10 MHz you will have to add a 15MHz lowpass filter. Therefore, you have to have a bunch of switchable lowpass filters and activate them based on what sinewave frequency you need to output.
With a DDS you only need one lowpass filter with the cut-off at 0.4...0.45  clock frequency of the DDS.

  Having multiple filters offers one serious advantage, it lowers THD+noise level down to unprecendented level, depends on order of the filters, of course,   5-9-th  would get -100 dBc.  There is no DDS capable to produce same qualilty sinewave, and OPA buffer is another story. Filters solved both problems at once - DDS limitation & OPA's.

 Recently I was considering to buy cheap 50-60-100 MHz DDS generator, but after watching some video on ytube devoted quallity of the signal, I dicided not to. 

Cost is another advantage.   This makes me wander, why those guys stubbornly follow FPGA + DAC route, instead of $1 PLL + bunch of LC filters for a penny ?

because "$1 PLL + bunch of LC filters for a penny " won't always do the job

[iMo]

because "$1 PLL + bunch of LC filters for a penny " won't always do the job

..like to change its output frequency X million times per second..

[tjadwy]

It seems there are a lot of AD9910 modules on market

[langwadt]

because "$1 PLL + bunch of LC filters for a penny " won't always do the job

..like to change its output frequency X million times per second..

or unless you are really  quick with the soldering iron, just every few minutes

[MasterT]

because "$1 PLL + bunch of LC filters for a penny " won't always do the job

..like to change its output frequency X million times per second..

 Don't remember I ever used this option on a Rigol. Do you?

If frequency FDMA required, usually it's not 0-1 GHz, for up to half band (extrem case, likely 20MHz is the most) LC w/o colonizer's FPGA still works better.

[iMo]

.. and ie. with the AD9912 (I still have gathering dust in my junkbox) you may change its sine output frequency, from say 350.000.000,000.000Hz to 350.000.000,000.004Hz (provided your 1GHz clock is of some quality) 

[MasterT]

.. and ie. with the AD9912 (I still have gathering dust in my junkbox) you may change its sine output frequency, from say 350.000.000,000.000Hz to 350.000.000,000.004Hz (provided your 1GHz clock is of some quality) 

There is no integer divider, so fractional PLL, just gives you false illusion, in reality freq. is jumping up and down as freaking horse. Phase - same things

Talking about those 50-60-100 MHz AWG they sample about 6 msps anyway, not many changes carrier possible, definitely below 1 MHz, switching filters could  do the same .

[radiolistener]

.. and ie. with the AD9912 (I still have gathering dust in my junkbox) you may change its sine output frequency, from say 350.000.000,000.000Hz to 350.000.000,000.004Hz (provided your 1GHz clock is of some quality) 

DDS will give you very high jitter for fractional frequencies. The frequency will jump so high from cycle to cycle, that it even don't have sense to mention these 0.04 Hz. Because you can see these 0.04 Hz only on averaging over very long time, where clock source stability make all these digits false and useless...

PLL with multisynth and square output and LC LPF allows to get much more clean and stable sine with mich lower noise floor and higher dynamic range

FY6800 with it's 4 ns jitter (which is extreme high) is example of DDS and FPGA+DAC limitations.

[iMo]

.. and ie. with the AD9912 (I still have gathering dust in my junkbox) you may change its sine output frequency, from say 350.000.000,000.000Hz to 350.000.000,000.004Hz (provided your 1GHz clock is of some quality) 

DDS will give you very high jitter for fractional frequencies. The frequency will jump so high from cycle to cycle, that it even don't have sense to mention these 0.04 Hz. Because you can see these 0.04 Hz only on averaging over very long time, where clock source stability make all these digits false and useless...

PLL with multisynth and square output and LC LPF allows to get much more clean and stable sine with mich lower noise floor and higher dynamic range

FY6800 with it's 4 ns jitter (which is extreme high) is example of DDS and FPGA+DAC limitations.

It is not 0.04Hz but 0.000004Hz, or 4 microHertz. That is the tuning step with 48bit frequency tuning word and 1GHz clock.

The phase accumulator of the DDS generates a DAC value (the sine), with output frequencies closer to clock/2 the number of the "sine DAC's output voltage points approximating the sine" goes down, sure. Therefore you have to use a DDS to to generate output freq up to clock/3 only (ie 300MHz in this example) in order to minimize the spurious in the spectra..

.. and ie. with the AD9912 (I still have gathering dust in my junkbox) you may change its sine output frequency, from say 350.000.000,000.000Hz to 350.000.000,000.004Hz (provided your 1GHz clock is of some quality) 

There is no integer divider, so fractional PLL, just gives you false illusion, in reality freq. is jumping up and down as freaking horse. Phase - same things

Talking about those 50-60-100 MHz AWG they sample about 6 msps anyway, not many changes carrier possible, definitely below 1 MHz, switching filters could  do the same .

Not sure what you are talking about.. We talk here "DDSes" only.. There are no PLLs involved, no jumping frequencies..

[radiolistener]

Not sure what you are talking about.. We talk here "DDSes" only.. There are no PLLs involved, no jumping frequencies..

PLL based synthesizers with square output working with clock in GHz range, it allows to minimize jitter. This is why si5351 output is much more clean than any DDS or FPGA+DAC solution.

The issue here is that frequency on DDS output will jump up and down on every cycle. In average for a long time you will get expected frequency value, but actually its frequency jumping up and down around expected one. This is why DDS output is very dirty and has many spurs. And you cannot improve it with filter, like you can do with PLL synthesiser with square output (si5351,adf4351, etc)