Please, advice cheap DDS up to 200MHz

[Gerhard_dk4xp]

What color is the sky on your home planet?

The phase increment of a DDS is correct to any arbitrary precision from
reference clock to reference clock and therefore the output frequency is
stable to any arbitrary precision.

The only unavoidable errors result from the imperfections of the D/A-
converter, and only if you insist in going to the analog domain.

[langwadt]

Not sure what you are talking about.. We talk here "DDSes" only.. There are no PLLs involved, no jumping frequencies..

PLL based synthesizers with square output working with clock in GHz range, it allows to minimize jitter. This is why si5351 output is much more clean than any DDS or FPGA+DAC solution.

The issue here is that frequency on DDS output will jump up and down on every cycle.

no it will not, the output is not a squarewave, it is points on sine wave with the resolution of the DAC

[radiolistener]

The phase increment of a DDS is correct to any arbitrary precision from
reference clock to reference clock and therefore the output frequency is
stable to any arbitrary precision.

No. The frequency error depends on ratio between signal frequency and DAC sample rate.
Since DDS has fixed and pretty low sample rate, it leads to pretty high frequency error which can be seen as high phase jitter on the output.

Since DAC output is discrete in time, many frequencies just don't fit with DAC time aperture. And you cannot fix it with precise phase increment.

[MasterT]

What color is the sky on your home planet?

The phase increment of a DDS is correct to any arbitrary precision from
reference clock to reference clock and therefore the output frequency is
stable to any arbitrary precision.

The only unavoidable errors result from the imperfections of the D/A-
converter, and only if you insist in going to the analog domain.

This is a mistake. It 'd be so if sine LUT has unlimited size, but in reality just 2-10 kBytes. If division of the master freq. and required output freg. is not an integer than each read cycle of the LUT table has discontinuity "jumps" and strictly speaking freq. resolution is quite low, especialy at high freq. sine wave. It visible on FFT charts as "aliasing" spikes

[radiolistener]

no it will not, the output is not a squarewave, it is points on sine wave with the resolution of the DAC

No, this is not about square/sine. This is about DAC time resolution which is discrete and can be changed only at fixed points of time, it prevents to get any frequency. It can produce stable frequency which is integer ratio with DAC sample rate, for all other frequencies you will have phase error, which is visible as phase jitter on DAC output.

This phase jitter is due to discrete and limited time aperture of DAC.
You can't fix it with more precise fractional phase increment, just because DAC don't allows to change value between clock pulses.

You can check it for any DDS on oscillocsope. The phase jitter is pretty visible.


The same issue is present on PLL+Multisynth with square output, but since they internally working at GHz frequency, they have much more smaller phase error.

DDS phase error is limited with DAC sample rate which is usually just several hundreds of MHz, this is why DDS has much worse phase noise.

This is why radio receiver with LO on PLL+Multisynth is more clean, has better dynamic range and less spurs. While the same radio receiver with LO on DDS is more noisy and has more spurs.

[langwadt]

no it will not, the output is not a squarewave, it is points on sine wave with the resolution of the DAC

No, this is not about square/sine. This is about DAC time resolution which is discrete and can be changed only at fixed points of time, it prevents to get any frequency. It can produce stable frequency which is integer ratio with DAC sample rate, for all other frequencies you will have phase error, which is visible as phase jitter on DAC output.

This phase jitter is due to discrete and limited time aperture of DAC.
You can't fix it with more precise fractional phase increment, just because DAC don't allows to change value between clock pulses.

it does not need to change values between clock pulses, at each clock pulse the dac outputs the correct sine value for that point in time

[psyon]

https://gra-afch.com/catalog/rf-units/dds-ad9910-arduino-shield/
https://gra-afch.com/catalog/rf-units/dds-ad9959-arduino-shield-rf-signal-generator-600-mhz-1-5-ghz-core-clock-low-spurs-low-harmonic/

Not sure what you considere cheap, but I have those two.

[radiolistener]

it does not need to change values between clock pulses, at each clock pulse the dac outputs the correct sine value for that point in time

You're wrong. High phase jitter is well known issue of DDS or DAC generators.

It don't needs to change output between clock pulses in case when you're generate sine which frequency is integer ratio of DAC clock frequency. For example if your DAC has 2 Hz sample rate and you're trying to generate 0.5 Hz sine it is ok, because 2/0.5 = 4.0 which is integer.

But this is not the case when you're trying to generate 0.7 Hz sine when DAC sample rate is 2 Hz, because 2/0.7= 2.857142857 which is not integer.

The reason for that is that in order to get precise phase you're needs to change DAC output at precise time intervals. But since DAC output is changed with fixed clock, you're stick with clock limitations.

For example let's assume DAC is clocked with 2 Hz, its output can be changed 2 times per second. In other words you can change DAC output with 0.5 second interval. And output bandwidth of this DAC is 1 Hz, so you can generate frequencies up to 1 Hz.

Now let's see what happens when you're trying to generate 0.7 Hz sine on that DAC. The period is 1/0.7 = 1.428571429 seconds. You're needs to change DAC output at least 2 times within this interval (two half periods), so you're needs to change DAC output each 1.428571429/2 = 0.714285715 sec. But DAC don't allow that period update. When you update DAC with 2 Hz sample rate you will get 0.714285715 - 0.5 = 0.357142857 sec error. As result you will not be able to get clean 0.7 Hz.

Your DAC output will jump between 0.5 and 1 Hz. You will get 0.7 Hz in average over long time period, but in fact the DAC output frequency will jump between 0.5 Hz and 1 Hz.

This is phase jitter. And this is well known issue of DDS generators. You can see this phase jitter on oscilloscope and on spectrum analyzer as mentioned above.

Higher DAC sample rate leads to smaller phase error, but if you generate signal with frequency close to the DAC Nyquist bandwidth the error will raise. And since topic starter needs 180 MHz signal it requires at least several tens GHz DAC sample rate in order to keep phase error small enough for a frequnecy which is not integer ratio to sample rate. But usual DDS DAC working below 200 MHz, so there is no way to get clean sine with that frequency with no significant jitter and high distortions.

When you use PLL synthesiser like si5351 or adf4351, it has programmable frequency multiplier inside in order to get clock in GHz range and then divide it to get expected frequency. It allows to minimize phase error. And such synthesizer has much more clean and stable output than DDS. It produce square wave, but the only thing that you needs to get sine is just to apply simple low pass filter to cut off harmonics.

I tested some DDS and si5351 and can confirm that si5351 has much more clean output.

[gf]

But this is not the case when you're trying to generate 0.7 Hz sine when DAC sample rate is 2 Hz, because 2/0.7= 2.857142857 which is not integer.

For 0.7 Hz, the DDS would output the samples marked with orange dots in the attached plot. And the reconstruction filter after the DAC will reconstruct the sine wave from these discrete samples.

It is a regular Shannon-Nyquist reconstruction of a (bandwidth-limited!) continuous signal from its discrete samples. It does not work if you violate the sampling theorem (the most prominent example for such a violation is the attempt to reproduce an ideal square wave with a DDS, by loading the wavetable with a [ +1, +1, +1, ... -1, -1, -1, ...] pattern).

[radiolistener]

For 0.7 Hz, the DDS would output the samples marked with orange dots in the attached plot. And the reconstruction filter after the DAC will reconstruct the sine wave from these discrete samples.

In order to get good reconstruction, you're needs to use DAC clocked at much higher sample rate and using interpolator. Such DAC with internal interpolator really exists they used in SDG2042X generator for example, but they are very expensive and their sample rate is more than 1 GHz.

With simple low pass reconstruction filter and DAC clocked at low sample rate (2 Hz in our example) you cannot get good reconstruction from these points (for 0.7 Hz in our example). It's almost impossible due to physical limitations of analog circuits.

It is a regular Shannon-Nyquist reconstruction of a (bandwidth-limited!) continuous signal from its discrete samples.

Your red dots really consists enough information to reconstruct the sine from math point of view and you can reconstruct it in digital domain, this is possible because we know that DAC bandwidth is limited with exact value of sample rate/2. But the problem here is that you cannot do that reconstruction in real analog circuit due to analog circuit limitations. It will require to increase DAC sample rate and do reconstruction in digital domain by applying up-sampling conversion with apply FIR filter in order to make it possible to get good result with analog reconstruction filter in real circuit.

This is why there is invented DAC's with internal interpolator which can do that job for you in order to get better signal reconstruction. But they working with GHz clock. And I didn't hear about DDS chips which can do the same for 200 MHz signals.

In order to get good reconstruction result, you're needs to use DAC sample rate about 10 times higher than your signal bandwidth. For sine with frequency up to 200 MHz it requires DAC with about 2 GS/s sample rate. In reality it may be even higher.

For example Siglent SDG2000X uses 1.2 GS/s DAC but it's output is limited with just 120 MHz and close to 120 MHz it's signal reconstruction is still not good enough.

With cheap si5351 moudle which cost about 2 USD and simple LPF, you can get much more stable and clean 180 MHz sine than using Siglent SDG6022X signal generator on FPGA+DAC running at 2.4 GS/s with 16 bit resolution which cost 1600 USD...

[iMo]

The DDSes (I've worked with) operate with a "phase accumulator" where you put the frequency word (ie 48bit long with the high-end chips).

The freq word (uint64)Fword = uint128(Fout*(2^48))/uint64(Fclock)   //with the 9912

Note: this calculation has been implemented mostly wrongly (especially with the famous 9850/51 etc in many designs, as you must use the 64bit integer math with 9850/51, for example).

At each Fclock edge (ie 1GHz, let us assume it is an ideal source) the accumulator adds the Fword to the previous value of the accumulator, and it does so in modulo 2^48 in a loop.

The DAC (ie 14/16bit with the high end chips) is "wired" to the accumulator (such it produces the "sine").
Note: it is not so with the high end chips (as they use some additional DSP subsections in between to minimize spurious, aliases, idle tones.. whatever) and the DAC's output follows the 1GHz clock.

So every 1ns you get a new DAC value at the output. The closer the Fout is to the Fclock/2 the less "points" the DAC is producing.

Now, the question is how the DDS frequency resolution (those 4 microHertz in case of the 9912) and the moment when the "rising edge of the DAC point" comes out are precisely related..

[gf]

Now, the question is how the DDS frequency resolution (those 4 microHertz in case of the 9912) and the moment when the "rising edge of the DAC point" comes out are precisely related..

"4µHz" is just rounded. Actually, the resolution is 3.552713678800500929355621337890625 µHz (i.e. sample_rate / 2^phase_accumululator_bits), and all frequencies which can be generated by the DDS are integer multiples of this resolution. Any other frequency would require a non-integer phase accumulator increment (or Fword, as you call it).

EDIT: This implies, however, that e.g. 100Mhz cannot be generated exactly with a 1GSa/s clock.
Fword = 28147497671065 results in   99,999,999.99999786913394927978515625 Hz and
Fword = 28147497671066 results in 100,000,000.00000141561031341552734375 Hz
(with 48-bit phase accumulator)

[iMo]

Normally you do not have exact Fclock=1GHz, but a number you know off a measurement you do, like 999.997.836,282.456 with a better meter
So those "4uHz" is just a placeholder for the discussion on how the DDS actually works.

I do not know how the 4uHz is related to the exact position of the "DAC output point" against the Fclock's rising/falling edge, I would be happy to know more.

PS: all ADI's DDSes since 9851 up have got an onchip PLL multiplier for the Fclock generation. We do not consider that here. Let us assume we feed the Fclock from an external 1.0GHz clock, none jitter.

[gf]

Normally you do not have exact Fclock=1GHz, but a number you know off a measurement you do, like 999.997.836,282.456 with a better meter
So those "4uHz" is just a placeholder for the discussion on how the DDS actually works.

The relative error of ~3.5e-15 due to the limited resolution is certainly much lower than relative clock frequency error of a typical clock (say 1ppm).

I do not know how the 4uHz is related to the exact position of the "DAC output point" against the Fclock's rising/falling edge, I would be happy to know more.

Why should the delay between DAC clock edge and point in time where the DAC outputs the next sample's value be related to the DDS frequency resolution? The DDS generates a continuous stream of samples, and the DAC outputs this stream of samples. If you are lucky, the delay is specified in the datasheet.

[radiolistener]

phase error can be up to ±0.5 = 1 sample interval. For 100 MS/s it will be 1/100M = 10 ns. For 1 GS/s it will be 1/1G = 1 ns.
This is pretty high phase noise and can be easily detected on oscilloscope.

Why should the delay between DAC clock edge and point in time where the DAC outputs the next sample's value be related to the DDS frequency resolution?

The issue is that DAC cannot fit it's sample time aperture with signal period. So, if you have sine which frequency ratio to sample rate is not integer, the beginning of every sine period will have time error ±0.5  sample. Technically you can try to adjust amplitude by taking into account for time shift error, but such way is limited with amplitude resolution of DAC so there will be always some degree of error.

In addition every DAC has it's own jitter and clock source also has some jitter. And amplitude resolution has some non-linearity. All this will make signal even worse...

[iMo]

Guys, my current understanding is as follows:

Imagine Fclock=1GHz exactly and rock stable.
You set a Fout.
You sync your scope on the rising edge of the Fclock.
You watch the DAC output and you zoom in at a DAC "point".

I think you will/may see the DAC point moving vertically, as the phase will/may change (the "phase accumulator" content will be changed at each Fclock).

Mind the DDS knows the "phase" increment only. The phase accumulator grows up by an (up to) 47bit large increment each clock, and it increments modulo 2^48.

So those multiplies of "4uHz" resolution will be visible as a drift of the phase of the "DAC sine point" against the leading edge of the Fclock.
The resolution of the movement (vertically) will be 16bit in case of the 16 bit DAC (in case of the raw DAC output, not filtered or DSP-ed).
With the reconstruction filter after the DAC you will see a monotonic smooth movement.

Or something like that..

PS: how fast the DAC point will be moving vertically depends on how far your 1ns is from exact (1/4uHz*K)

[gf]

The issue is that DAC cannot fit it's sample time aperture with signal period. So, if you have sine which frequency ratio to sample rate is not integer, the beginning of every sine period will have time error ±0.5  sample.

It does not matter where the period starts. It can start anywhere between samples, and each period can start at a different fractional position between samples. The sine wave (or the ARB wave you want to generate) is (re)sampled by the DDS with constant phase increment, even across period boundaries, and the phase increment does not need to be an integer fraction of 2*PI. If the frequency ratio is not an integer, then different periods are sampled at different phases.

Think of it as if the DDS would do something like this:

    phase = 0
    for each each sample
    {
        value_of_sample = sin(phase)
        phase = (phase + phase_increment) % (2 * PI)
    }

In practice, the phase accumulator is an integer, say 48-bit, and the phase range 0...2*PI is represented by values 0...2^48. If the phase accumulator holds a value of (say) 12345, this corresponds to phase = 12345 / 2^48 * 2 * PI.

In practice, the DDS also does not calculate sin(phase) for each sample, but it does a table lookup. A table size of 2^48 entries is not feasible, so we have to live with a smaller wavetable, for example with 65536 or 2^16 entries. In order to map the phase accululator range 0...2^48 to 0...2^16, we need to divide by 2^32 (which is trivial for binary numbers) in order to find the index of the table entry which corresponds to the phase accumulator value. The question is, what do we do if the remainder of the division is not zero?

(1) We simply ignore the remainder and accept the resulting error. This is called "phase truncation".

(2) Alternatively we can use the remainder to interpolate between adjacent table entries. Since the table is usually large, even linear interpolation works reasonably well. The literature also proposes several other methods to improve accuracy which are even beyond simple interpolation.

In the frequency domain, phase truncation error leads to spurs.
See https://www.analog.com/media/en/technical-documentation/application-notes/an-1396.pdf

[ejeffrey]

phase error can be up to ±0.5 = 1 sample interval. For 100 MS/s it will be 1/100M = 10 ns. For 1 GS/s it will be 1/1G = 1 ns.
This is pretty high phase noise and can be easily detected on oscilloscope.

Why should the delay between DAC clock edge and point in time where the DAC outputs the next sample's value be related to the DDS frequency resolution?

The issue is that DAC cannot fit it's sample time aperture with signal period. So, if you have sine which frequency ratio to sample rate is not integer, the beginning of every sine period will have time error ±0.5  sample. Technically you can try to adjust amplitude by taking into account for time shift error, but such way is limited with amplitude resolution of DAC so there will be always some degree of error.

Nope.  This is just a misunderstanding of the relationship between the time and frequency domain.  What you are descriing is basically looking at the time domain points and mentally drawing a curve through them, then saying it doesn't follow the ideal sine wave.  This is not how it works.

If you have a sufficiently accurate lookup table and a reconstruction filter that rejects the first alias, then there is no phase noise / spur limit to a DDS.  In your example of a 2 Hz DAC producing an 0.7 Hz signal, the first alias is at 1.3 Hz and you do need a relatively sharp filter if you want good rejection of that signal.  And normally you do: non-harmonically related spurs are usually far worse than harmonics.  But is easy to calculate how good it needs to be, and if you instead want to produce 0.4 Hz with the same sample clock it's much easier.

In addition every DAC has it's own jitter and clock source also has some jitter. And amplitude resolution has some non-linearity. All this will make signal even worse...

Sure there are imperfections in a real circuit from DAC non-linearity and sample clock jitter.  But that's different than a fundamental problem with DDS.  A bigger issue is that many cheap DDS generators have pitifully small lookup tables and no interpolation.  Truncation of tuning word at the DDS lookup table is the biggest problem in cheap DDSes because it creates close in spurs and low frequency spurs that can't be filtered.  These spurs can be reduced with phase dithering, but that adds phase noise so you really want to start with the best sin/cos tables you can.    And yes this becomes an issue with very small frequency steps like the 200 MHz + 100 uHz example.  Without a very good sin/cos function you will indeed end up with a cluster of spurs around the target frequency rather than a single line.  But if you increase the size of your lookup table that becomes less and less of an issue.

[iMo]

..
Note: this calculation has been implemented mostly wrongly (especially with the famous 9850/51 etc in many designs, as you must use the 64bit integer math with 9850/51, for example)..

The app note above stresses the need to make the math with the pretty large integer values properly. Some 25years back when the first hobby DDSes designs appeared people did the math with 9850/51 (32bit phase accumulator) in 32bit integer or later 32/64b floating point which led to large freq errors. I did the same at that time and my VCOs were quite off. So I had to introduce 64bit uint multiply and divide into my pic16 in order to get expected results. With the 48bit ph. accumulators you need 128bit uint mul/div to be happy.

PS: there were even happy designs where you calculated a single fixed value for "your frequency step" - like "Fword_1Hz" usually, and with the rotary encoder you incremented/decremented the initial ph. accumulator value by that step. Imagine the errors after dialing up by say 20MHz..

[radiolistener]

The issue is that DAC cannot fit it's sample time aperture with signal period. So, if you have sine which frequency ratio to sample rate is not integer, the beginning of every sine period will have time error ±0.5  sample. Technically you can try to adjust amplitude by taking into account for time shift error, but such way is limited with amplitude resolution of DAC so there will be always some degree of error.

Nope.  This is just a misunderstanding of the relationship between the time and frequency domain.  What you are descriing is basically looking at the time domain points and mentally drawing a curve through them, then saying it doesn't follow the ideal sine wave.  This is not how it works.

If you have a sufficiently accurate lookup table and a reconstruction filter that rejects the first alias, then there is no phase noise / spur limit to a DDS.

I don't see where did you found "misunderstanding", things you're talking about is mentioned in quote on which you respond. Here it is:

Technically you can try to adjust amplitude by taking into account for time shift error, but such way is limited with amplitude resolution of DAC so there will be always some degree of error.

But this way, as I already said and as you're explained above, is also limited with amplitude resolution of DAC, include amplitude error due to LUT size limitations and rounding error during truncate to limited bits count of amplitude resolution.


As I already said - yes, from theory point of view you can do good reconstruction in math. But in reality it is limited with analog circuit limitations for reconstruction filter and limitations for DAC amplitude resolution, include limitations for LUT tables, as you correctly mentioned, it also add some degree of error.

Due to physical limitations it is impossible to ideally reconstruct analog signal from digital discrete representation. You can make it more precise by using more complicated scheme which requires more computational power and higher clock frequencies. It all makes circuit much more expensive, but you never get ideal reconstruction from digital to analog. It's just impossible.

And even if you try to make it more and more complicated to get better precision, at some point you will catch fundamental limitations of our world, for example due to thermal noise and quantum limits.

[Nova_PA]

wow wow!
I didn't expect that my question will grow to such a big duscussion!

Colleagues!
You sent me a few links to the modelling boards which i see really expensive.

I need something to build getherodyne for VHF maring band (156 - 160 MHz)...

[iMo]

..I need something to build getherodyne for VHF maring band (156 - 160 MHz)...

For that you have to indicate your IF1, IF2.. frequencies. You are not going to mix with 156-160MHz VFO (aka direct conversion), as you indicate above.
The closest DDS chips are those with 500MHz clock, such you get 0-160MHz VFO.
But it depends on your IF frequencies, with several IFs you will need several oscillators - VFO/BFOs etc. as well..
There is an option to use PLL based VFO, which costs nothing and it may work fine in your application.
Like the Si5351 mentioned above, which can create 3 independent frequencies for your superhet.
I am not aware of any single band VHF radio produced in last 25++years for that band which uses DDS, imho. Perhaps large all-band rigs (HF+VHF+UHF)..

[MasterT]

Awhile ago I experimented with Si4432 module from ali-china-market. They have likely some clones for you band freq., Si4463
with description tag like "433Mhz SI4463 HC-12 Wireless Serial Port Module 1000M Replace For Bluetooth"

[Nova_PA]

I am not aware of any single band VHF radio produced in last 25++years for that band which uses DDS, imho. Perhaps large all-band rigs (HF+VHF+UHF)..

Maybe You're right... I'm looking for a cheap solution for receiving on a fixed frequency (or tuning within very small range) on VHF
Can really use two convertions by one si5351 chip?
For example, IF1 80 MHz - filtering - and already low frequency

[Nova_PA]

Could You tell more? Due I see in datasheet - thic IC starts from 240 MHz...