I am designing a board around the Mini-Circuits PMA5-63-2W+ GaAs power amplifier, and I need help designing the hardware power-sequencing circuit.
Since this is a depletion-mode GaAs device, it requires a strict power-on sequence to prevent destroying the internal FETs:
V_G1 = -2V(Pinch-off)
V_G2 = +5V
V_DD = +12V
Adjust V_G1 to target I_DD approximately 400mA
On power-off, this sequence must be reversed V_DD drops before V_G1 collapses.
I want to ensure hardware protection so that +12V, V_DD can never turn on if V_G1 fails or drops below -1.8V.
Question: I could design something that does this "from scratch" but would appreciate guidance as to how this can be best achieved.
Aspects that I would hope would be covered by answers include but are not limited to the following:
Achieving the cleanest, most reliable circuit to implement this hardware interlock? (e.g., Voltage supervisor/comparator driving a high-side PMOS on the +12V line vs. dedicated sequencer ICs?)
Suggestions re any off-the-shelf bias/sequencer ICs (like Analog Devices or similar) that you I can use to design a sequencer for multi-rail depletion-mode RF MMICs?
Guidance as to how you typically handle power-off discharge rates to ensure V_DD bleeds off faster than V_G1?
Any schematic snippets or proven reference designs would be greatly appreciated!