Author Topic: Synthesized Clock Gen. (Stanford Research Systems CG635) teardown + analysis  (Read 838 times)

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Online D StraneyTopic starter

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Here's an interesting instrument I came across at work: it's a programmable frequency synthesizer that can produce programmable frequencies from 1 uHz to 2.05 Ghz.  Besides the normal test equipment features you'd expect (can lock to a 10 Mhz input, has GPIB and RS-232 controls), it's got complementary outputs with programmable voltage levels for different logic standards.  So with something this flexible, I badly wanted to have a look inside: luckily, there were no calibration or warranty stickers, and the top half was held on by only 4 screws on the sides, so it was easy to take a quick non-destructive peek and snap some photos.



About half of the space inside the case is taken up by the massive power supply: there's more things going on with the main board underneath the power supply, but in the interests of disturbing this expensive piece of equipment, which I don't own, as little as possible, those will have to forever remain a mystery (unless I can get my hands on an awesome eBay deal for one of these, that is).  I honestly don't know quite what it needs such a large power supply for.  The optional internal rubidium reference clock probably takes some power, and I can imagine that driving a lot of approximately-20-year-old digital circuitry (especially ECL, as we'll see later) at up to 2.05 Ghz takes a reasonable amount of power considering all the capacitive loads and such, and there are probably at least a few different output voltages, but still, this feels excessive.  Here's where it connects down to the main board:


Let's start with the more obvious functional pieces.  Next to the power supply output, near the front of the unit, is a control section with a mystery TI processor - I haven't been able to track down the exact part from the markings, strangely enough.

Next to that is the output board, which directly connects to the BNC output connectors.  Top 2 BNCs are the full-range complementary outputs, while the bottom BNC is a CMOS-only output that only goes up to 250 Mhz.

The 2 QFN chips here are both Maxim MAX3737E, a high-speed laser diode driver with adjustable current.  I thought the parallel between the choice of this chip here for a non-laser-diode high-speed driver application, and the same use of a laser diode driver in Leo Bodnar's pulser, was interesting: I guess if fast optical comms is the place with the most high-volume demand for high-speed drivers with lots of output current, then it makes sense to repurpose the chips developed for that in other applications with similar requirements.  It looks like one of these chips is used to drive the complementary outputs directly.  You can see the large 24.9-ohm output resistors and what looks like possibly an RC differential load (the two tombstoned components with the horseshoe of wire in between) across the two outputs.

At the bottom, near the CMOS output BNC, are two sets of high-speed bipolar transistors: the BFG541 and BFG31 (9 Ghz and 5 Ghz, NPN and PNP).  These likely drive the CMOS output directly.  I'm guessing the two pairs are either arranged as cascaded amplifiers, or paralleled for extra drive current.  Based on position, this second MAX3737E may do the base drive/level-shifting for the CMOS output - even if nothing else, producing the complementary outputs for the push/pull base drive signals seems useful...and hey, it was on the BOM already.

Most of the rest of the output card circuitry consists of slow op-amps (LM358, LF353) and adjustable regulators (LM317, LM337).  I'm guessing these are responsible for producing variable supply voltages for the output stages, to provide the adjustable output voltage levels.  There's an LTC2620 at the very bottom right, on the main board next to the output card's connector: this is a 12-bit 8-output DAC, and likely produces (among other things) the setpoint voltages used for the adjustable regulators.  The one thing on this output card that I'm not sure about is the LM7171; it's a fast op-amp (200-220 Mhz for gains of +1 to +2) so far faster than needed for the adjustable supply voltages, but also too slow for even the CMOS output (up to 250 Mhz square wave).


In the middle of the main board there's a mystery section:

You can see two symmetrical sections side by side: each one has...
  • A large film capacitor (1uF polypropylene/MKP)
  • a crystal of unknown frequency
  • AD8561 fast comparator (7 ns)
  • a mystery SOT23-5 next to the comparator (either AND on left/NOR on right, or both various LDO possibilities, based on my searches)
  • LM358 dual op-amp
  • Misc. filtering, including an inductor
Any insights into what this section does would be appreciated.

Anyways, let's not dwell on that too much.  Next to it is a DDS chip, the AD9852, with an output transformer and a few stages of output harmonic filtering:

However, the AD9852 only can do 300 Msps maximum - even if you only care about getting a square wave out of it (no filtering on the output, or bad spectral purity), this only gets you 150 Mhz at most.  Where does everything from 100-ish Mhz to 2.05 Ghz get generated?

Well, that seems to come from this other section, between the DDS chip and the front panel:


The main parts of the high-frequency synthesizer are that metal can, the QFN chip directly above it, and the SSOP to the top-right of that (marked "F4106").  These parts are, in order:
  • A Z-comm V585ME48-LF VCO, with a range of 950 Mhz to 2.05 Ghz
  • A ridiculously fast comparator (ADCMP567, 250 ps): this probably takes the VCO's sinewave output and produces a nice digital output
  • An ADF4106 frequency synthesizer controller; this basically has every part of a PLL frequency synthesizer (programmable prescalers, phase comparator, charge pump for VCO control, misc. other functions) except the VCO itself
So the ADF4106 wraps a loop around the VCO+comparator and can generate frequencies from 950 Mhz to the top of this instrument's range (2.05 Ghz).  But where does everything from 100-something Mhz to 950 Mhz come from?

Check out the circuitry in that second photo, and at the bottom-right of the first photo.  The quad-flatpack is an ECL 8-bit counter, which seems to get its "preset" input value from a digital latch over by the main processor; there's also an ECL D-FF and 2 ECL JK-FFs.  The output of that fast comparator (the ADCMP567) gets picked off by some series RC circuits for the ADF4106's sensing, and then goes over to directly clock one of the D-FFs, whose output clocks the 8-bit counter; this "direct" (un-divided) clock runs downwards and enters one of the pairs of inputs on that "100...EP57" ECL 4:1 mux at the bottom.
Meanwhile, both the original clock and the carry output of the counter seem to go and connect to an interesting arrangement of the J-K FF and D-FF below the counter.  I can't see all the traces of course, but since the ~Q output of the D-FF connects to both J and K inputs on the J-K FF (00 = no change, 11 = toggle on clock), my best guess is that this completes the programmable frequency divider formed by the 8-bit counter: using the carry output of the counter as a selectable "toggle" vs. "don't toggle" control, it can produce a nice 50%-duty-cycle square wave from the low-duty-cycle carry-output pulses (with an extra divide-by-2 factor).
So that 4:1 mux at the bottom can select one of a few clock signals: the straight VCO output (950 Mhz+), maybe VCO output / 2 through the top-left D-FF, and VCO output  divided by programmable ratio (which covers the frequency range between the DDS's max. capabilities, and the bottom of the VCO's range at 950 Mhz).

So if you have a pretty capable frequency synthesizer circuit like this, why would it even need that Analog Devices DDS chip in the first place?  Well, producing an output frequency that can go down to 1 uHz from a 950 Mhz-minimum VCO would be kind of crazy.  An 8-bit programmable divider on the high-frequency output is one thing, but a 50-bit (!) programmable divider would be a whole different matter.  Considering that precision low-frequency generators are comparatively easy to build anyways, there's just no need for the Stanford Research engineers to put themselves through that kind of design.  Additionally, because it's easier to get precision out of low-frequency generators anyways, the low-frequency ranges can probably have much better stability etc. if they're fed from their own dedicated source, rather than from an insanely-divided-down high-frequency source.  Now I haven't looked into the specifics of doing a design like this in detail, but that's my best guess.

Here's a parting shot of the rear-panel section, where the 10 Mhz inputs/outputs are, and the optional internal frequency reference attaches, with what looks like some isolating transformers:
 
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