bench logic analyzer

[mian2zi3]

There has quite a bit of discussion on USB logic analyzers (Saleae and the like), but not so much on bench top analyzers.  I have a few projects in mind where 16 channels isn't going to cut it (microprocessor data and address bus with control signals in addition to IO, etc.)  I'd like something that could eventually watch DDR(2).  My budget is around $1k, although somewhat flexible.  I was looking at the Agilent 16702B and Tek TLA714.  It seems like I might be able to pick up a TLA715 in that range, although the active and completed eBay listings vary pretty wildly in price, so I'm not sure what I can reasonably expect to pay.  Anything else I should consider?  Any traps to watch out for?  Thanks!

[John_ITIC]

I have a HP/Agilent 16700B and a couple of 16702B's. These can be picked up cheaply on Ebay but I doubt you'll be able to pick up a DDR2 probe on Ebay. If you are building a system in FPGA then there are tools included that allows you to bring the DDR2 interface up without use of external logic analyzer.

With the SignalTap/Chipscope now included in the FPGA tools, I find my logic analyzers mostly gathering dust. one exception is when I need to capture very long data sequences. I then bring out signals to Mictor connectors via Altera Logic Analyzer Interface (LAI). The scope probes then connects directly to the Mictor connectors.

What exactly will you use the LA for?

[marshallh]

You won't get anything turnkey for that price. Probing ddr2 properly requires a BGA interposer with embedded chip resistors, basically a grid of Zo probes built into the substrate.

Once you have the signals brogut out you can  use any of the 16700 series with fast enough timing capture. You are going to be less interested in state capture since DDR2 involves things going on each side of the clock and also out-of-phase DQS strobes and DQ alignment. You need at least 2x oversampling for this.
With 1GHz timing capture you should be good up to DDR2-800, but may not be able to see some things, which is a scopes speciality.

[mian2zi3]

I have a HP/Agilent 16700B and a couple of 16702B's. These can be picked up cheaply on Ebay but I doubt you'll be able to pick up a DDR2 probe on Ebay. If you are building a system in FPGA then there are tools included that allows you to bring the DDR2 interface up without use of external logic analyzer.

With the SignalTap/Chipscope now included in the FPGA tools, I find my logic analyzers mostly gathering dust. one exception is when I need to capture very long data sequences. I then bring out signals to Mictor connectors via Altera Logic Analyzer Interface (LAI). The scope probes then connects directly to the Mictor connectors.

What exactly will you use the LA for?

Thanks for the reply!

So it sounds like using a LA on DDR2 isn't realistic or necessary.  I've been using Xilinx ISE, which doesn't include ChipScope unfortunately.  I'm just a hobbyist and Vivado is not cheap.  It looks like the Web version of Quartus does include SignalTap if you enable TalkBack, so maybe I should think about using Altera parts.

The current project I have in mind is to debug/reverse engineer/reimplement a microprocessor board (8-bit, few MHz) in a modern FPGA.  I am aiming to be cycle-accurate, so I was also planning to use the LA to compare the two boards running in parallel.

I'm also working on my first board with DDR + FPGA.  I hoped I would be able to work up to DDR2 and could use a LA (and scope of course) for debug.

[nctnico]

I have a TLA704 + TLA7N4 module (500Ms/s 200MHz syncronous max) for sale which has been more or less upgraded to TLA714 performance level (see buy/sell/wanted section). It is ready to go but shipping (around 110 euro) could be a killer.
A nice upgrade would be a TLA7AAx module which has a higher sampling rate and even more memory. Only the probes are less easy to interface. At high speeds you don't want to use flying leads so you either have to go for a Mictor connector or attach the probe to the board directly.

[codeboy2k]

...Probing ddr2 properly requires a BGA interposer with embedded chip resistors, basically a grid of Zo probes built into the substrate.

I had to look it up, having never used a BGA interposer before.  CAD $1672 for a Keysight DDR4 interposer! 
http://www.keysight.com/en/pd-2452352-pn-N2115A/ddr4-bga-interposers?cc=US&lc=eng

Does this DDR4 interposer have embedded resistors?  it's not clear... it looks like just a PC board with signals brought out on matched lengths.

[nctnico]

IMHO there is a much better way around this. DDR memory can also run at lower clock speeds. This is before the memory's PLLs are enabled. That way you can run somewhere at 50 to 80 MHz for which you don't need fancy probing.

Then again: why would you need to debug a DDR memory interface? Most modern FPGAs have a built in DDR memory controller which needs configuring. As long as the PCB layout is according to the PCB design guidelines you should be OK. If not you are dealing with signal integrity problems for which a logic analyser is not the right tool.

[joeqsmith]

I use the 16702B.  I have some deep memory, fast differential cards for it along with some low end  single ended cards.    It's big and heavy.   But I really like using it.  Easy to control from Ethernet.    It's all about the cards.

At home I currently have an old HP1663C.   Single ended, shower (I think 500MHz interlaced), no color CRT.   More than enough channels for what I need.  For FPGAs I embed the LA (Chipscope).   

[John_ITIC]

IMHO there is a much better way around this. DDR memory can also run at lower clock speeds. This is before the memory's PLLs are enabled. That way you can run somewhere at 50 to 80 MHz for which you don't need fancy probing.

Then again: why would you need to debug a DDR memory interface? Most modern FPGAs have a built in DDR memory controller which needs configuring. As long as the PCB layout is according to the PCB design guidelines you should be OK. If not you are dealing with signal integrity problems for which a logic analyser is not the right tool.

Good points. In my experience, DDR2 in speeds available in mid-level FPGAs (up to around 300 MHz) is very forgiving timing-wise. No special attention needs to be made with regards to board layout, length matching etc as specified in the DDRx specs. For maximum clock frequency (say, 800 MHz and higher) timing on the board and I/O, however,  becomes very critical. I believe DDR2 has a minimum clock frequency of around 125-150 MHz so that may be where you have to start).

If you want to create your own DDR/DDR2 IP Core then you are in for a lot of hard work. I know there are free cores for SDR, DDR and DDR2 on Opencores.org or the like but these are usually so badly documented so hard to make work. Therefore, for professional projects, commercial DDR2/3 cores like included in Quartus II subscription are recommended.