Rigol MHO98 Teardown

[PELL]

Haven't been here for a long time , I don't browse this forum much often now.

Rigol just launch their new scope MHO98 and MHO900 series, thanks to my friend "依人如梦言如许", we now have an inside look of MHO98

[PELL]

According to my firmware analysis, the main processing chip is a rebranding FPGA from Fudan Microelectronics, part number is FM230T. They make 1:1 Xilinx compatible FPGA

[jackcheng]

大佬速度就是快

[0xdeadbeef]

At least no crusty trimmers in the frontend. Interesting though that the input stages of the four channels are not totally symmetrical. It looks like 1+3 are the same and 2+4 are the same, but e.g. 1+2 differ.

[Martin72]

The front-end chips, ADCs, and “CPU” are the same as in the DHO800....DHO4000(DHO800...DHO100 1 ADC, DHO4000 2 ADCs).
The two relays per channel in the front end indicate a 50-ohm input, although I cannot find any corresponding resistors.
But I hadn't found it in the DHO4000 teardown pictures either, too blind I guess.

edit correction of ADCs.

[voltsandjolts]

According to my firmware analysis, the main processing chip is a rebranding FPGA from Fudan Microelectronics, part number is FM230T. They make 1:1 Xilinx compatible FPGA

Fudan were blacklisted by the US a few days ago, but AFAIK that only restricts export of American equipment to them, not imports of their products. Maybe Rigol branded it just in case .

[TurboTom]

The front-end chips, ADCs, and “CPU” are the same as in the DHO800....DHO4000(DHO800 1 ADC, DHO1000 2 ADCs, DHO4000 4ADCs)
The two relays per channel in the front end indicate a 50-ohm input, although I cannot find any corresponding resistors.
But I hadn't found it in the DHO4000 teardown pictures either, too blind I guess.

Small correction: There's one ADC in the DHO1000 and two in the DHO4000. So this hardware is probably very close in performance and configuration to the DHO4000 plus the additional digital interface. Seems Rigol also included a battery-backed RTC on this board. I'm quite curious how "well" this device performs sampling-rate-wise with the digital channels enabled... 

[Martin72]

Thanks, I´ve corrected it.
I don't know how I got the idea that the 4000 has 4 ADCs, but a glance at the picture makes it clear that there are only two:
https://www.flickr.com/photos/eevblog/52393925309/in/album-72177720302521598/

But now help a blind man out, where did Rigol hide the 50 ohms?
With Siglent and Co, they are quite easy to identify because they are quite large SMD resistors and then 2x 24R9 or 25 ohms.

[0xdeadbeef]

Maybe on the other side, but the resolution of that image is not high enough to be sure.

[MadTux]

According to my firmware analysis, the main processing chip is a rebranding FPGA from Fudan Microelectronics, part number is FM230T. They make 1:1 Xilinx compatible FPGA

So it's Xilinx fallen out of a truck that went to laser engraver or true cold war style 1:1 silicone clone?
Or spec sheet clone, new design that is binary compatible?

[2N3055]

Maybe on the other side, but the resolution of that image is not high enough to be sure.

I took a look at 4000 pics. There are no termination resistors on either side. It could be that front end chip is directly terminating input. That would be fun for overloads...
 
P.S. Took another look.

First relay chooses 50Ω or 1MΩ path.
There seem to be 2 50Ω inputs on chip, actually 2 paths that are switched by 2nd relay together with corresponding PI attenuators.
50Ω is DC coupled all the time.  1MΩ path goes to PhotoMOS and capacitor for AC/DC coupling. All range switching
for 1MΩ is solid state in frontend chip.

There are no external termination resistors. Front end chip is terminating.

[Martin72]

Thank you, so I'm not blind after all, because I had searched through all the images I could find.

That would be fun for overloads...

Oh yes, instead of replacing a resistor, it's the IC's turn—a disaster for the customer.
One can only hope that Rigol has incorporated appropriate safety measures, because it is easier than one might think to “overdrive” the 50-ohm input.
Do I believe that? No...

[PELL]

According to my firmware analysis, the main processing chip is a rebranding FPGA from Fudan Microelectronics, part number is FM230T. They make 1:1 Xilinx compatible FPGA

So it's Xilinx fallen out of a truck that went to laser engraver or true cold war style 1:1 silicone clone?
Or spec sheet clone, new design that is binary compatible?

From a trusty source: Fudan actually got Xilinx's help when making these chip, Fudan now even has some RFSoC clone. And it's not made by TSMC!

My personal guess is: At first, Fudan was trying to reverse engineering Xilinx FPGA then sell it to defense related company in China, but the result wasn't ideal. At the same time, Xilinx also wants to sell FPGA to these companies, but due to obvious reason they can't sell it directly.

Then somehow Fudan convince Xilinx to help them build the clone chip, and now both Xilinx and Fudan make big buck of money out of this, it's basically a win-win deal from company standpoint.

Note: I don't want to involve politics in this topic

[jackcheng]

the ADC is same model with the one in DHO800, except it has 2 ADC. How is the 4GSa/s is calculated? Is it means 2G per ADC then multiple 2=4GSa/s? Does that prove that the DHO800 serials can "update" to 2GSa/s and 1G bandwidth? Is there anyone knows who has hacked the sample rate of DHO800 serials before?

[eurofox]

the ADC is same model with the one in DHO800, except it has 2 ADC. How is the 4GSa/s is calculated? Is it means 2G per ADC then multiple 2=4GSa/s? Does that prove that the DHO800 serials can "update" to 2GSa/s and 1G bandwidth? Is there anyone knows who has hacked the sample rate of DHO800 serials before?

You should ask norbert.kiszka, he is currently hacking the DHO800/900 

[thm_w]

the ADC is same model with the one in DHO800, except it has 2 ADC. How is the 4GSa/s is calculated? Is it means 2G per ADC then multiple 2=4GSa/s? Does that prove that the DHO800 serials can "update" to 2GSa/s and 1G bandwidth? Is there anyone knows who has hacked the sample rate of DHO800 serials before?

Its sequential sampling, yes 2G per ADC, then add the data together for 4.

DHO800 will be limited by the front end bandwidth and the processing power of the CPU/FPGA. It has a different lower power part than DHO1000 and this MHO98 I assume. I'm not sure if we have any details on this "RT6888IF" IC.

[Martin72]

The CPU is not included in this comparison, as the DHO800 has the same CPU as the DHO1000 and DHO4000 (Rockchip 6-core).
FPGA could be another one, and as already mentioned, the front end might not even be capable of operating at up to 1 GHz.

You should ask norbert.kiszka, he is currently hacking the DHO800/900

And you can pay for it.

[Fungus]

At least no crusty trimmers in the frontend. Interesting though that the input stages of the four channels are not totally symmetrical. It looks like 1+3 are the same and 2+4 are the same, but e.g. 1+2 differ.

There's 2 ADCs so maybe the difference is to multiplex them.

eg. 1+2 might be on one ADC and 3+4 on the other.

[ptluis]

At least no crusty trimmers in the frontend. Interesting though that the input stages of the four channels are not totally symmetrical. It looks like 1+3 are the same and 2+4 are the same, but e.g. 1+2 differ.

There's 2 ADCs so maybe the difference is to multiplex them.

eg. 1+2 might be on one ADC and 3+4 on the other.

SDcard as booting device, so booting time around 80 secs? will this be a standard on newer oscilloscopes?

[0xdeadbeef]

eg. 1+2 might be on one ADC and 3+4 on the other.

This would be a typical layout, but I saw a video that claimed that any two channels could be uses in 2ch mode.
Then again, who knows. Might be also a wrong display of sampling rate and memory due to firmware bugs.
After all, the displayed sampling rate also doesn't seem to change when adding the LA channels.

[2N3055]

the ADC is same model with the one in DHO800, except it has 2 ADC. How is the 4GSa/s is calculated? Is it means 2G per ADC then multiple 2=4GSa/s? Does that prove that the DHO800 serials can "update" to 2GSa/s and 1G bandwidth? Is there anyone knows who has hacked the sample rate of DHO800 serials before?

First thing first, ADC is just ADC. It is not self clocked.

So you have external clock source, and FPGA. Both of those are tailored for 1.25GS/s clock rate and corresponding data volume.

[NE666]

After all, the displayed sampling rate also doesn't seem to change when adding the LA channels.

Since the LA section uses its own high speed comparators and not the analog front ends' ADCs then, assuming the FPGA/CPU have enough grunt, LA sampling could be interleaved with the analog to maintain the sample rate of the latter.

[0xdeadbeef]

Since the LA section uses its own high speed comparators and not the analog front ends' ADCs then, assuming the FPGA/CPU have enough grunt, LA sampling could be interleaved with the analog to maintain the sample rate of the latter.

The problem here is that there is nothing specified about the LA sampling rate or memory  in the MHO900/MHO98 data sheets and actually also not in any other Rigol data sheet I looked at.
The LA on Siglent scopes uses its own sampling rate and memory, but this doesn't seem to be the case for recent Rigol scopes. At least for the DHO900 line, activating the LA reduces sampling rate and memory just as if an additional analog channel was activated. I.e. there are resources shared with analog channels, mainly memory but obviously also (memory/transfer) bandwidth.
As many others, I would have assumed that this is also the case on the MHO900/MHO98. But obviously activating the LA doesn't show the same effect on sampling rate and memory there as on the DHO900. I.e. activating one channel and the LA still shows 4GSa/s and 500 Mpts just as without the LA.
Now, the question is: does the MHO900/98 really have a different architecture there or is it just a firmware bug that leads to not displaying the effect on sampling rate and memory correctly?

[Fungus]

Might be also a wrong display of sampling rate and memory due to firmware bugs.
After all, the displayed sampling rate also doesn't seem to change when adding the LA channels.

Logic channels don't go through the ADC so why should the sample rate drop... 

The unusual thing is why it does drop on other devices. It must be a limit on the FPGA or something in those models. Maybe they require the data to be interleaved with the analog samples and this one doesn't.

(Was that the idea behind the DHO900's extra RAM chips but it never got implemented...?)

[0xdeadbeef]

Logic channels don't go through the ADC so why should the sample rate drop... 

As I suggested in the posting you quoted, I suggested memory/transfer bandwidth.
If there is no dedicated LA memory, the main acquisition memory must be used. So, most obviously, the memory depths for analog channels is reduced.
But also memory/transfer bandwidth that is usually used for an analog channel is used by the LA in this case.
I.e. the memory/transfer bandwidth is reduced for analog channels and hence the sampling rate drops.