Upgrading DSLogic Basic to Plus without EEPROM modification

[webhdx]

The firmware file is in HEX format and the file itself is 44kB: https://github.com/podonoghue/LogicAnalyser/blob/master/Software/fx2lafw_eeprom_loader/bin/DsLogicPro Most of the contents are 0xFF's so it will probably just write first 16kB of the file. This is what worked for me.

I think you are right and it's just a firmware for USB stuff, not actual bitstream for FPGA. Yes I've heard about the drama between sigrok and DsView. The UI in DsView is terrible on Mac, there are lots of issues - I can't really zoom with mouse scroll etc. PulseView is what it is but at least I can comfortably use it on macOS.

[robca]

Great. I can confirm that this file  https://github.com/podonoghue/LogicAnalyser/blob/master/Software/fx2lafw_eeprom_loader/bin/DsLogicPro is, indeed, identical to the DsLogic Plus Cypress firmware, so it can be used to convert a U2Basic to Plus. And th eone you found is easier to find than all other semi-hidden files

What confused me in your reply, is that actually in the DsView distribution there is a file called DsLogicPro.bin (334K) and a DsLogicPro.fw (8k). The bin file is the hdl that DsView uploads upon initialization (and so does PulseView when manually adding those files), and the fw file seems to be a Cypress firmware, but very different from the one used on the Plus. There is an utility hex2bin that can easily convert between hex and bin formats and makes it easy to compare the different formats.

If anyone does a search for DsLogicPro.bin, they will find the wrong file, and that was the source of my confusion. I would suggest that you edit your great summary, and add the github URL of the actual file you used, to help future readers.

[Prehistoricman]

Thanks to everyone in this topic who worked this stuff out.
I just bought a U2Basic and completed the upgrade to Plus. I used hot air, a microscope, and scalpel to lift that FPGA pin. Still not a difficult mod IMO. Here's a pic of the board after lifting the pin and adding a wire.

I dumped the memory from the EEPROM and found it to be different to what sigrok says on their wiki: https://sigrok.org/wiki/DreamSourceLab_DSLogic_U2Basic
Mine has 7000 bytes instead of 6977.
I didn't use the USB utility to reflash the EEPROM, though I now realise that would have been the easier option. I used an Arduino-based programmer and one of those SOIC clips which had a surprisingly dicky connection.

Also I noticed that, after changing the EEPROM, I couldn't capture any waveform in DSView until I added that missing address wire.

[elBundinio]

Hi,

I just dismantled my DSLab Basic that I bought a long time ago and discovered that it doesn't have any ram at all. Might this explain why I've had such difficulty getting it to work or were some of these things actually supposed to ship with no ram?

Anyway, I've ordered a MT48LC8M16A2P-6A from rs-components so I'll solder that on when it turns up and see how I get on from there.

[robca]

Hi,

I just dismantled my DSLab Basic that I bought a long time ago and discovered that it doesn't have any ram at all. Might this explain why I've had such difficulty getting it to work or were some of these things actually supposed to ship with no ram?

Anyway, I've ordered a MT48LC8M16A2P-6A from rs-components so I'll solder that on when it turns up and see how I get on from there.

You have one of the older Basic, not the U2Basic which is discussed here. In your case, soldering the RAM and changing a few bits in the EEPROM is all you need, no FPGA surgery. Much easier than converting the U2Basic

[fonak]

Hello

New version of DSview has been released: v1.2.0 — (2022-07-05)

https://www.dreamsourcelab.com/download/

ChangeLog
—————–
–common
*fix issue of large file saving failure in some cases
*optimize file saving speed
*fix issue of recognization of USB2.0 devices under MacOS
*fix abnormal window display caused by system scaling
*fix issue of hidden toolbar buttons
*fix assert errors caused by multithreading problem
*modify processing window of file saving
*fix accidental operation issues during file loading
*fix screenshot issue
*build a new compilation method based on cmake
*fix window cannot be recoved issue after moving out of screen
*fix other display issues

–for logic analyzer
*add protocol search function
*add auto stacking function when adding multi-layer protocols
*optimize decoder memory usage
*add specific decoder support for format conversion of data
*add enable/disable options for mouse quick scroll
*add csv export format selection (original / compressed)
*fix issue of wave back search
*optimize parallel decode, and increase to 32 data channels
*optimize the clock edge setting of MDIO decoder
*fix issue of Flexray decoder
*fix issue of ps/2 decoder
*optimize sdcard decoder
*extend interval to 0.1s under repeat mode
*increase number of decoders up to 138

–for oscilloscope
*fix the data accuracy issue when exporting csv file
*fix math waveform generation of half screen data when stop
*remove invalid edge count measurment display
*fix crash caused by trigger dock movement
*fix display error of time ruler in some cases

–for data acquisiton
*fix data inverval error under ultra-low sample rate

[cobramostar]

if I buy a new fpga, since I broke the pin on the existing one that needed to be raised, is there a file that needs to be inserted into it (fpga) and how can I use which HW

[robca]

if I buy a new fpga, since I broke the pin on the existing one that needed to be raised, is there a file that needs to be inserted into it (fpga) and how can I use which HW

The necessary bitstream is downloaded in the FPGA every time you start DsView. Assuming it's cost effective to buy a new FPGA vs buying a new device, replacing the FPGA is safe to do.

If you have a Dremel tool with a fine tip and a good stereo microscope, you can also probably remove enough of the FPGA package material to expose the pin again. The sliver of silicon inside a FPGA is small, and there is plenty of pin material inside the package. I mean, that FPGA is toast for your purpose anyway, so might as well try to save it. Something like https://www.reddit.com/r/electronics/comments/75wcjb/how_to_repair_an_ic_with_damaged_pins/

For everyone else attempting this modification, be aware that damaging the FPGA pins is a real possibility

[cobramostar]

is there a difference in the family if this one is from 2013, but I can find it in 2005

https://de.aliexpress.com/item/1005004024791617.html?spm=a2g0n.detail.1000014.4.7e0c4658vTgIio&gps-id=platformRecommendH5&scm=1007.18499.332340.0&scm_id=1007.18499.332340.0&scm-url=1007.18499.332340.0&pvid=5a318a3d-f810-4540-b6dc-5082e05db8e8&_t=gps-id%3AplatformRecommendH5%2Cscm-url%3A1007.18499.332340.0%2Cpvid%3A5a318a3d-f810-4540-b6dc-5082e05db8e8%2Ctpp_buckets%3A668%232846%238109%231935&pdp_npi=4%40dis%21BGN%2133.68%2133.01%21%21%2118.00%21%21%402103146c16956427935132733e047b%2112000027783341628%21rec%21BG%21137681740%21&gatewayAdapt=glo2deu

[robca]

is there a difference in the family if this one is from 2013, but I can find it in 2005

https://de.aliexpress.com/item/1005004024791617.html?spm=a2g0n.detail.1000014.4.7e0c4658vTgIio&gps-id=platformRecommendH5&scm=1007.18499.332340.0&scm_id=1007.18499.332340.0&scm-url=1007.18499.332340.0&pvid=5a318a3d-f810-4540-b6dc-5082e05db8e8&_t=gps-id%3AplatformRecommendH5%2Cscm-url%3A1007.18499.332340.0%2Cpvid%3A5a318a3d-f810-4540-b6dc-5082e05db8e8%2Ctpp_buckets%3A668%232846%238109%231935&pdp_npi=4%40dis%21BGN%2133.68%2133.01%21%21%2118.00%21%21%402103146c16956427935132733e047b%2112000027783341628%21rec%21BG%21137681740%21&gatewayAdapt=glo2deu

Protip: don't buy an FPGA from an Aliexpress seller with 90% rating. Desoldering and resoldering that many pins risks damaging the PCB, and you don't want to discover you got a bad FPGA (or even a different chip with altered markings) after soldering it (and having to remove it again)

Use a reliable source like https://www.digikey.com/en/products/detail/amd/XC6SLX9-2TQG144C/2339919 or similar

But, yes, if you want the device to work as expected, use the exact same device model or you risk that either the bitstream doesn't work or subtle timing differences prevent the logic analyzer from working properly

[lyxmoo]

Protip: don't buy an FPGA from an Aliexpress seller with 90% rating. Desoldering and resoldering that many pins risks damaging the PCB, and you don't want to discover you got a bad FPGA (or even a different chip with altered markings) after soldering it (and having to remove it again)

NOT terrible as above description,  but NO select cheapest seller， what price, what goods 。

[cobramostar]

first attempt

[robca]

Looks promising.

I had good luck with this wire for super-tiny soldering jobs https://www.remingtonindustries.com/magnet-wire/155-c-polyurethane/?_bc_fsnf=1&Wire+Size%5B%5D=40+AWG&Wire+Size%5B%5D=44+AWG. The coating is easily burnt off with a slightly hotter soldering iron, and the wire is easily solderable after that, with the coating still protecting the rest of the wire. I solder/strip 2-3mm, then snip to leave only a short solderable section of the wire.

[ic3_2k]

Looks like there is new hardware on the DSLogic U2Basic

The FPGA is no more a Spartan6 now is a PANGO PGL12G somebody knows if it can be upgraded too?

[robca]

You will need to trace the connections between the memory and FPGA, but without the exposed pins, I doubt you'd be able to make this work.

Worse: in order to make DSView recognize the hacked U2Basic as a Plus, you need to change the device ID so that DSView can upload the right FPG bitstream. The new FPGAs use a different bitstream, so you'd also need to figure out if there is a U2Basic and Plus for the PANGO, and change the device ID that way

So, all considered, unlikely it will work unless you can get both a new U2Basic and new Plus, and figure everything else out...

[mwb1100]

I don't know exactly how helpful this might be:  I believe support for the Pango was added in this commit to DSLogic's github (https://github.com/DreamSourceLab/DSView.git):

Code: [Select]

C:\devtrees\DSView>git bugnote 2532ad4c1
```
in repository: C:/devtrees/DSView
in branches:  master
============
commit 2532ad4c
Author: dreamsourcelabTAI <tzz@dreamsourcelab.com>
Date:   Mon Dec 12 15:58:05 2022 +0800

    Suports new hardware

A       DSView/res/DSLogicPlus-pgl12.bin
A       DSView/res/DSLogicU2Basic-pgl12.bin
M       libsigrok4DSL/hardware/DSL/command.h
M       libsigrok4DSL/hardware/DSL/dsl.c
M       libsigrok4DSL/hardware/DSL/dsl.h
============
```

And in case it helps, the Pango firmware files have been updated in these commits:

Code: [Select]

C:\devtrees\DSView>git ls -- DSView/res/DSLogic*-pgl12.bin
264e7c46 DreamSourc.. 2023-06-27  update FPGA bin files (version E)
b9b143c3 DreamSourc.. 2023-06-16  update fpga bin file for DSLogic
63955d72 dreamsourc.. 2023-04-26  Loop mode
cfa0c1cb dreamsourc.. 2023-01-12  update: new firmware file
2532ad4c dreamsourc.. 2022-12-11  Suports new hardware


[robca]

I don't know exactly how helpful this might be:  I believe support for the Pango was added in this commit to DSLogic's github (https://github.com/DreamSourceLab/DSView.git):

Code: [Select]

C:\devtrees\DSView>git bugnote 2532ad4c1
```
in repository: C:/devtrees/DSView
in branches:  master
============
commit 2532ad4c
Author: dreamsourcelabTAI <tzz@dreamsourcelab.com>
Date:   Mon Dec 12 15:58:05 2022 +0800

    Suports new hardware

A       DSView/res/DSLogicPlus-pgl12.bin
A       DSView/res/DSLogicU2Basic-pgl12.bin
M       libsigrok4DSL/hardware/DSL/command.h
M       libsigrok4DSL/hardware/DSL/dsl.c
M       libsigrok4DSL/hardware/DSL/dsl.h
============
```

And in case it helps, the Pango firmware files have been updated in these commits:

Code: [Select]

C:\devtrees\DSView>git ls -- DSView/res/DSLogic*-pgl12.bin
264e7c46 DreamSourc.. 2023-06-27  update FPGA bin files (version E)
b9b143c3 DreamSourc.. 2023-06-16  update fpga bin file for DSLogic
63955d72 dreamsourc.. 2023-04-26  Loop mode
cfa0c1cb dreamsourc.. 2023-01-12  update: new firmware file
2532ad4c dreamsourc.. 2022-12-11  Suports new hardware


Could still be possible, but one needs to EEPROM values for the new U2Basic and Plus. The right ID is needed so that DsView can decide to send the new bitstream instead of the old.

From the picture, it seems that the line A12 is connected in the memory chip (pin 36). If so, that means that the hardest part (lift the FPGA pin to add the address wire/pin) is not needed on this new device. A low risk test should be possible: rename the FPGA bitstream for the new Plus bitstream as the U2Basic (so that DsView sends the Plus bitstream thinking it's sending the U2Basic), capture data to fill the memory of the Plus, and monitor the A12 line. If there is activity in the A12 line, it might be possible to perform the hack by replacing the memory and finding the right ID for the EEPROM (by asking a new Plus user to read their EEPROM, which can be done without opening or any risk to their device)

If A12 is tied to ground like it was in the Spartan U2Basic, the hack is probably too hard...

[Pandor]

Just wanted to share another success story.
Thanks to all who contributed to the cause.

[profrook]

Could still be possible, but one needs to EEPROM values for the new U2Basic and Plus. The right ID is needed so that DsView can decide to send the new bitstream instead of the old.

From the picture, it seems that the line A12 is connected in the memory chip (pin 36). If so, that means that the hardest part (lift the FPGA pin to add the address wire/pin) is not needed on this new device. A low risk test should be possible: rename the FPGA bitstream for the new Plus bitstream as the U2Basic (so that DsView sends the Plus bitstream thinking it's sending the U2Basic), capture data to fill the memory of the Plus, and monitor the A12 line. If there is activity in the A12 line, it might be possible to perform the hack by replacing the memory and finding the right ID for the EEPROM (by asking a new Plus user to read their EEPROM, which can be done without opening or any risk to their device)

If A12 is tied to ground like it was in the Spartan U2Basic, the hack is probably too hard...

Just got mine U2Basic today, with PGL12G FPGA.
The USB device ID is in the commit.

Code: [Select]

    {0x2A0E, 0x0030, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic PLus", NULL,


Code: [Select]

    {0x2A0E, 0x0031, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U2Basic", NULL,

Btw, anyone found anything on they new FPGAs?