(MIPS 1994) Algorithmics P4000: Tech Doc, Memory Map, RAM Controller Details

[DiTBho]

Algorithmics P4000: Technical Documentation, Memory Map, and RAM Controller Details

Hi everyone,
As part of a retrocomputing and educational hardware preservation project, I am currently working on resurrecting an Algorithmics P4000 MIPS evaluation board (from around 1994, featuring the 72-pin SIMM sockets, a SONIC Ethernet controller, an ST Timekeeper RTC, and an IDT chipset).

Since complete, structured documentation online is scarce, I was wondering if anyone in the community has (or knows where to find) a digital, scanned, or transcribed copy of the P-4000 User's Manual or related hardware specs.

Specifically, I am looking for information regarding:

Maximum Addressable Memory & EDO Support: What is the hard limit for the onboard SIMM slots? Has anyone ever successfully run EDO RAM on this board, or is it strictly limited to Fast Page Mode (FPM) DRAM?

RAM Controller Jumpers: Are there any undocumented or documented jumpers or configuration pins on the board/RAM controller (e.g., to handle interleaving or tweak memory timings)?

Complete Memory Mapping: A breakdown or summary of the physical address map for the board's main devices, including:

Main DRAM mapping (and uncached/cached segments)
+ ROM / Boot EPROM space
+ Serial ports registers
+ Ethernet controller (SONIC)
+ RTC / NVRAM (MK48T02B Timekeeper)

Any hints, pointers, or old notes you might be willing to share would be hugely appreciated to help bring this board back to life.

Thank you very much for your time and expertise 

[squadchannel]

https://web.archive.org/web/20020806030010/http://www.algor.co.uk/algor/info/p4k-benefits.html

P-4000i hardware features

    CPU: NEC R4200, R4400PC, R4000PC, or R4600, 3.3 or 5V, at input frequencies between 40-75 MHz. This represents a range of CPU power somewhere around 35-70 SpecInt.
    All R4x00s are fully compatible with user-level software from 32-bit MIPS CPUs (R3000), but add a complete 64 bit instruction set.
    Various configurations are jumper-selectable, including the ``little-endian'' mode. However, software will have to adapt appropriately.

    Main memory: from 4 - 96 Mbytes 64-bit wide, parity-protected DRAM using four slots for industry-standard 36-bit SIMMs, fitted in pairs. This is nearly as efficient an R4x00 memory as can be implemented without interleave, with access latency of 120ns at the CPU pins and burst bandwidth of 200Mbytes/s.

    PROM: 2 × 8-bit, 512Kbyte PROM sockets. The CPU can run cached from a single 8-bit PROM, facilitating the use of PROM emulators.

    Ethernet interface: ``thick-wire'' interface using a NatSemi ``SONIC'' controller. Supports fast download and host access, essential for a good development environment.

    Other I/O: non-volatile memory and real-time clock, dual serial ports, 4-character LED display for diagnostic and debug messages. Two 32-bit timers are available for real-time functions. Custom logic speeds interrupt handlers.

    Daughterboard interface: a 150-way connector implements a 64-bit multimaster synchronous bus, clocked at 33Mhz (independent of the CPU clock), and somewhat like a widened PC ``local bus''. DMA daughterboards can access P-4000i main memory.

    Traceability: The P-4000i can be put in a ``debug'' mode where all CPU cycles are reflected on the daughterboard connector (which can continue to function as an IO expansion bus). This allows the use of a logic analyser to follow addresses from the CPU in a last ditch effort to debug errant software, but without having to track 50Mhz signals.

and a lot of info in this page!!!!!!

https://web.archive.org/web/19970711005111/http://www.algor.co.uk/algor/info/ftplist.html

https://web.archive.org/web/20020118094338/http://www.algor.co.uk/ftp/pub/hardware/p4000i/

[DiTBho]

Has anyone ever used this board?