2MHz 6502, vs 7MHz 68000
and his comment was based on real hardware his unit built running software his team wrote - so i trust him.
I don't believe it.
6502 takes 1 clock cycle per byte read/write (including instruction fetch), with a minimum of 2, plus 1 extra for a taken branch, or for a carry (page crossing) during indexed addressing or branch offset calculation.
68000 takes 4 clock cycles per byte or word read/write (including instruction fetch), plus 2 more for indexed addressing (each operand) or a taken branch.
So, on the face of it, it looks at first that a 2 Mhz 6502 and 8 MHz 68000 are going to have similar timings.
The problem is, the 6502 usually needs several instructions to do what the 68k can do in one.
For example, your commonly-used variables are usually in registers on 68k and in Zero Page on 6502. The 68k does a register-to-register add in 4 clock cycles (8 for a = b + c rather than a += b because it needs an extra move). The 6502 needs 11 cycles for 8 bit variables (CLC, LDA, ADC, STA) or 20 cycles for 16 bit variables.
If they were clocked the same and you only needed 8 bit variables then the 6502 would be not too far off. But that's not the case. The 68k is clocked 3 or 4 times faster.
What about memory block moves (often a limiting factor)?
The 68k typically does "move (an)+,(an)+; dbne" for 22 cycles for copying either a byte or a word at a time. (let's ignore 32 bits at a time, which is 30% faster again). 6502 typically does "lda (zp),y;sta (zp),y;dey;bne" for 15 cycles per byte assuming no page crossing. If you don't mind self-modifying code you can cut the 6502 time down by 2 cycles. Unrolling has a similar effect for both, so I'll ignore that.
So, again, if they were clocked the same and the 68k is restricted to byte-at-a-time then the 6502 is competitive .. even a little faster. But, again. the 68k is actually clocked 3 or 4 times faster.
I'm sorry, but I just don't see it.