.... I would be interested in a brief description of how the PIC firmware handles the interface with the 68008. For example, how are bus transactions detected?
Thanks!
Pete
Hi,
only two address lines (A1 and A0) are used, so you have 4 real I/O addresses. This allows to save MCU GPIO pins.
To allow more selections, an Opcodes "strategy" has been implemented.
The Opcodes are atomic operations that can be done by the CPU as "Virtual HW registers" managed by the FW inside the PIC.
With the Opcodes you have a "two stages" I/O operation, so at first you write the opcode wanted into the Opcode "register" (i.e. send a character to the serial port 2) and then make the data exchange writing (or reading) into the "Execute Opcode" register (can be a multi-byte operation as in the Virtual Disk Opcodes).
The memory mapped I/O address space depends on the HW configuration option that has been implemented (between Full or Lite).
In the Lite HW configuration option only the A19 is used to "switch" between the memory and I/O addresses, while in the Full HW option A15 to A19 are"sensed" to select a 16KB I/O area.
This seemed to me a good trade off between HW implementation and address space "consumption".
In any case only 4 I/O addresses are recognised, and are "mirrored" in all the remaining I/O address space.
The IO#/M signal is used to detect the I/O address space (see schematic) and this signal is an input of an internal logic function made with two CLC modules (a sort of LUT of a CPLD) inside the PIC to "stop" the CPU deselecting the DTACK signal (CLC generated).
This gives the time to the PIC to interface the CPU bus for the needed operation. The DS# and R/W# signals are used to recognise the bus operation (together with the INTA signal).
On the bus a combination of DTACK + HALT signals is used to avoid data clash, and this is the "heart" of the "virtual engine" of the FW inside the PIC.
The logic function inside the CLC is "dynamic" as it changes depending by which one between the Full or Lite HW option is implemented.
The FW can recognise it and changes the logic function at first as some signals work inverted in the Lite HW option.
Regards.
J4F