Apollo Guidance Computer based in NOR gates

[Picuino]

According to Wikipedia, the Apollo capsule's on-board computer was built with approximately 2800 integrated circuits of (mostly dual) three-input NOR gates using RTL technology.

Does anyone know how a CPU could be built using only three-input NOR gates?

https://en.wikipedia.org/wiki/Apollo_Guidance_Computer
https://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_logic

[TimFox]

Simple-minded answer:
Any logic function can be made from only NOR gates (or only NAND gates).
The inversion is necessary for either case to make all binary functions.

[iMo]

The guys at CuriousMarc mess with it for 7 years already..
In the Part #23 they were already flying it..

[UnijunctionTransistor]

Perhaps 15 years ago, I found a website which actually had some AGC schematics.
Really fascinating and artistic looking stuff. I even had one displayed as the wallpaper on my personal computer.

Let me see if I can find them again.

EDIT: found the web page. Study them and you'll appreciate the engineering tour de force that the Apollo program was.

https://klabs.org/history/ech/agc_schematics/

[Picuino]

What a mess of wires and logic gates!
I can see several feedback NOR gates, which form flip-flops and, I imagine, latches from them.

I seem to recall that the 8008 microprocessor had only 3500 transistors, another small miracle of technology: https://en.wikipedia.org/wiki/Intel_8008

I will have to read a book on microprocessor architecture to get an idea of how to build a CPU from logic gates, latches, and so on.

[cfbsoftware]

I will have to read a book on microprocessor architecture to get an idea of how to build a CPU from logic gates, latches, and so on.

I recommend the book "Digital Circuit Design" by Niklaus Wirth. You can download the table of contents from:

https://link.springer.com/book/10.1007/978-3-642-57780-2

[Picuino]

Digital Circuit Design for Computer Science Students - Niklaus Wirth

Perfect book! The book is short and introduces all types of circuits gradually, building up to explaining how to make a elementary computer with them all in chapter 8.

1. Transistors and Gates
1.1. Gates with Bipolar Transistors ............................................ 1
1.2. Gates with Field Effect Transistors ...................................... 5
1.3. Electrical Characteristics of Gates ....................................... 8

2. Combinational Circuits
2.1. Boolean Algebra .................................................................. 13
2.2. Graphical Notations ........................................................... 15
2.3. Circuit Simplification ......................................................... 15
2.4. The Decoder or Demultiplexer .......................................... 19
2.5. The Multiplexer ................................................................... 21
2.6. The Adder ............................................................................ 21
2.7. The Adder with Fast Carry Generation ............................. 25
2.8. The Multiplier ..................................................................... 27
2.9. The Read-Only Memory (ROM) ........................................ 28
2.10. The Combinational PLD .................................................... 31
2.11. The Programmable Gate Array ......................................... 34
2.12. Dynamic Behaviour of Combinational Circuits ............... 36

3. Latches and Registers
3.1. The SR-Latch ....................................................................... 39
3.2. The D-Latch ......................................................................... 41
3.3. The D-Register .................................................................... 43
3.4. The JK Register ................................................................... 46

4. Synchronous, Sequential Circuits
4.1. The State Machine .............................................................. 50
4.2. The Shift Register ................................................................ 52
4.3. The Synchronous Binary Counter ..................................... 53
4.4. A Design Methodology for State Machines ...................... 55
4.5. The PLD and the FPGA with Registers ............................. 60
4.6. Timing and Practical Considerations ............................... 62

5. Bus Systems
5.1. The Concept of a Bus .......................................................... 65
5.2. The Open-Collector Circuit ............................................... 66
5.3. The Tri-state Gate ............................................................... 68

6. Memories
6.1. Static Memories .................................................................. 71
6.2. Dynamic Memories ............................................................ 74
6.3. Dual-Port Memories ........................................................... 76

7. Formal Description of Synchronous Circuits
7.1. Motivation ........................................................................... 79
7.2. Lola: A Formal Notation for Synchronous Circuits ......... 81
7.3. Examples of Textual Circuit Descriptions ........................ 90

8. Design of an Elementary Computer
8.1. The Design of von Neumann ............................................. 95
8.2. Choice of a Specific Architecture ...................................... 98
8.3. The Arithmetic-Logic Unit (ALU) ................................... 100
8.4. The Control Unit ............................................................... 102
8.5. Phase Control and Instruction Decoding ....................... 104
8.6. An Implementation Using Standard Parts ..................... 107
8.7. Interrupts ........................................................................... 112

9. Multiplication and Division
9.1. Multiplication of Natural Numbers ................................ 118
9.2. Division of Natural Numbers .......................................... 122
9.3. Extending the ALU by a Multiplier-Quotient Register .. 126

10. Design of a Computer Based on a Microprocessor

11. Interfaces Between Asynchronous Units
11.1. The Handshake Protocol.................................................. 139
11.2. Processor-Bus Interfaces .................................................. 142
11.3. Adding an I/O Interface to the Hercules Computer ...... 144

12. Serial Data Transmission
12.1. Introduction ...................................................................... 147
12.2. Synchronous Transmission ............................................. 148
12.3. Asynchronous Transmission ........................................... 154
12.4. A Buffered Transmitter and Receiver ............................. 164

[Picuino]

But how on earth could they make a bus (with tri-state outputs) using only NOR gates?

[Picuino]

Interesting project:

Build an 8-bit computer from scratch
https://eater.net/8bit

[pqass]

But how on earth could they make a bus (with tri-state outputs) using only NOR gates?

They probably use open collectors; ie. not connecting the pullup resistor to Vcc on the NOR chip (see dark-tipped NORs in the schematic).

[Picuino]

That's right! RTL logic is based on a pull-up resistor that can be left unconnected to Vcc if you want.

All of this is quite handcrafted.

[pqass]

What a mess of wires and logic gates!

Zoom out, way out.
First understand the high-level architecture. See attached for an example.

You will see that there is a common bus with latch or buffer blocks taking a snapshot of the bus or placing a byte on it, respectively.
Each block has a control pin for LOAD and/or OE (like a '373 or a '244) and sometimes CLEAR.
The ALU is just combinational logic (gates like a '181; no clocked flip flops) with additional pins to select function (add, shift, neg, etc) and OE.
All of these control pins terminate at the wide data bus of the microcode ROM inside the Control Unit (however many data pins as latch+buffer control pins plus additionals).
The instruction register (IR) supplies the most significant address bits of the microcode ROM. 
The clock sequentially steps through the microcode ROM addresses however many steps to advance a finite state machine ({en|dis}abling latches and/or buffers to affect data movement). 

For example, see below for an implementation of:
  opcode = 0, no operation/fetch next instruction, and
  opcode = 16, move C into the accumulator and add 1
(IR+SUBADDR is the full address of the microcode ROM, the rest of the line are the data bits affected at that address)

Code: [Select]

IR=0 SUBADDR=0: PC.OE=T, MAR.LOAD=T, MAR.OE=T, MEM.CE=T, MEM.RD=T; all other data bits=F    // tee-up a MEM address to fetch MEM data
IR=0 SUBADDR=1: MEM.OE=T, IR.LOAD=T; all other data bits=F                                  // after MEM data returns one clock later, put it in IR
IR=0 SUBADDR=2: PC+1.OE=T, PC.LOAD=T; all other data bits=F                                 // update PC with the PC+1 register; latter is updated whenver PC.LOAD=T
IR=0 SUBADDR=3: IR.OE=T; all other data bits=F                                              // execute the new opcode in IR by jumping into the new IR+SUBADDR=0 in the microcode ROM
...
IR=16 SUBADDR=0: C.OE=T, Acc.LOAD=T, ALU.func=1111 (A+1 function); all other data bits=F    // move C to Acc and add 1
IR=16 SUBADDR=1: ALU.func=1111 (A+1 function), ALU.OE=T, Acc=LOAD; all other data bits=F    // move the ALU output (Acc+1) back into Acc
IR=16 SUBADDR=2: IR.CLEAR=T, IR.OE=T; all other data bits=F                                 // execute IR=0 which fetches new instruction byte from memory
...
I hope you get the gist.
Now translate all the latches, buffers, counters, gates into NOR logic, then into RTL!

[pqass]

For the AGC specifically, see this slide presentation for a good summary.
The detailed info can be found in this book. But a PDF can be found in the wild.

The closest to the AGC CPU achitecture diagram I've found is "Logical overview" on page 15 of the presentation above.
The CPU is a bit of a dogs breakfast; memory bank switching, one's complement, no stack (not sure), etc.

[cruff]

I highly recommend this book about the AGC development (both hardware and software): Journey to the Moon: The History of the Apollo Guidance Computer by Eldon C. Hall. (https://www.amazon.com/Journey-Moon-History-Guidance-Computer/dp/156347185X)

[brucehoult]

According to Wikipedia, the Apollo capsule's on-board computer was built with approximately 2800 integrated circuits of (mostly dual) three-input NOR gates using RTL technology.

Does anyone know how a CPU could be built using only three-input NOR gates?

Note that the Cray 1 used only logic chips with two NOR gates, one with 5 inputs and one with 4 inputs. And two different kinds of SRAM chips, one for registers and one for main memory.

It's kind of interesting that textbooks concentrate more on NAND gates.

[Picuino]

https://en.wikipedia.org/wiki/Cray-1

https://american.cs.ucdavis.edu/academic/readings/papers/CRAY-technology.pdf

https://bitsavers.trailing-edge.com/pdf/cray/CRAY-1/2240004C_CRAY-1_Hardware_Reference_Nov77.pdf

It seems incredible. I certainly didn't know that basic logic gates had been used so extensively in making computers as far back as 1976.

[harerod]

But how on earth could they make a bus (with tri-state outputs) using only NOR gates?

The AGC may not be the best system to get started with tricky designs. Sir Clive also showed a tricky/cheap way to glue devices together in the ZX Spectrum. 
. . . At any rate, looking at those AGC schematics makes the reason why NASA had to put Clint Eastwood's gang of oldtimers into orbit outright plausible. ("Space Cowboys", one of my guilty pleasures)

[amyk]

It's kind of interesting that textbooks concentrate more on NAND gates.

That's because NAND is preferred in CMOS designs: https://electronics.stackexchange.com/questions/110649/why-is-nand-gate-preferred-over-nor-gate-in-industry

[brucehoult]

It's kind of interesting that textbooks concentrate more on NAND gates.

That's because NAND is preferred in CMOS designs: https://electronics.stackexchange.com/questions/110649/why-is-nand-gate-preferred-over-nor-gate-in-industry

My textbooks (and university digital logic study) are from a time when CMOS existed but no one used it because 4000 series was WAY slower than 74LS.

And, as mentioned, both Apollo GC and Cray 1 used exclusively NOR gates.

Something that always makes sense, in a lesson/textbook environment is that it is conventional to design a lot of kinds of non minimised logic as a "sum of products" with a set of AND gates followed by a single OR gate to work with all the cases where the output is 1, and you can just replace them all with NAND and it works. If you wanted to use NOR gates then you'd be working with minterms (times when the output is low) not maxterms, and this seems less common.

[TimFox]

Original TTL and older DTL NAND structures were perhaps simpler to fabricate than NOR.
AOI (and-or-invert) TTL was also common.

[radiogeek381]

I know, I'm reviving this well after its "best if used by" date.   

Something that always makes sense, in a lesson/textbook environment is that it is conventional to design a lot of kinds of non minimised logic as a "sum of products" with a set of AND gates followed by a single OR gate to work with all the cases where the output is 1, and you can just replace them all with NAND and it works. If you wanted to use NOR gates then you'd be working with minterms (times when the output is low) not maxterms, and this seems less common.

That's likely true, but it isn't wasn't necessary.  I worked for a very long time in a design environment where mixed level logic was the standard practice. In that case, the circuit that is in the data book as a 2 input NOR functions as an OR gate with active high inputs and an active low output, or an AND gate with active low inputs and active high output.  (The idea is to make the mapping from T,F onto voltage levels a matter of choice. We indicated which representation was used by a _H suffix (T = H, F = L) or a _L suffix (T = L, F = H) on the signal name. )  Logical complement doesn't use any transistors - if an active high signal is connected to a bubble, then the logic sense is inverted.

I started designing this way in 1983 and haven't had to think about DeMorgan since then. It also made schematics much easier to understand and review: the pointy-boats and dull-boats actually say what they mean. (In full-custom, no synthesis design, schematic reviews were really important. Just because the simulator says it works doesn't mean it will.)

https://peer.asee.org/a-case-for-teaching-mixed-logic-in-digital-design.pdf is a very brief treatment, not as clean as I'd like, but serviceable. I taught from William Fletcher's text.

So, in the end, hardware components need not influence the choice of sum-of-products vs. product-of-sums.

But this is largely irrelevant in today's world of "write the verilog/vhdl and let cacence/synopsis/whoever sort it out."  Probably for the better.

[Picuino]

The Apollo Guidance Computer: Architecture and Operation

https://www.amazon.com/-/es/Apollo-Guidance-Computer-Architecture-Operation/dp/1441908765