confused, fpm vs edo, how to identify?

[DiTBho]

Hi,
I'm very confused. I need to install four SIM72 modules in an older X-Terminal, which, being MIPS-R3K-based, has an external RAM controller designed for FPM, and they must also be 50-60nsec, according to the documentation 70-80nsec won't work.

I don't think EDO modules will work there; the timing is slightly different from FPM, and here we are: I need to buy FPM modules.

But they are *very* expensive!

I received a very interesting offer: four Samsung KMM5368105BK-6 ("-6" means "60 ns") modules for $30 shipped

But I'm not sure if they're FPMs; they look like EDO, but how can I verify that remotely? I can't find the datasheet 

Is there a trick to identifying FPM/EDO from the chip label?

Thanks 

[SiliconWizard]

Well, looking it up, it is definitely listed as EDO with parity:
https://www.memory4less.com/samsung-32mb-simm-edo-kmm5368105bk-6

[DiTBho]

Next step, how to identify fpm modules to be bought

[SiliconWizard]

Looks like the above website has FPM sticks, and yes, they look more expensive than EDO for some reason, probably because they're older and rarer.

But as to being able to determine which is which by just looking at them, I don't think there's any foolproof way. They look identical. So unless it's directly marked on the sticks or you can find the info by looking up the exact PN or reference of the RAM chips, I don't know of any way you can tell for sure.

[DiTBho]

A lot of doubts about the FPM_with_EDO_mode to FPM backward compatibility

Anyway, thanks to a VPN, I found the datasheet.

[DiTBho]

There were many RAM controllers of that era that were designed to work with either.  Does the manual specifically say FPM only?

I can't find a digital manual to be uploaded here. I only have the paper manual of my Tektronix xp417, made in 1997, using a MIPS CPU manufacturered by LSI.

In 1997 machines were still moving from FPM to EDO, and R3K ram controllers were very sensitive about the ram timing.

[DiTBho]

The manual doesn't even mention "EDO".

[Zoli]

One possible source would be the HP Laserjet4 memory expansion modules. I have some 8MB modules left from a printer, but I have to dig them out....

[DiTBho]

What makes me confused is the datasheet title: "Fast Page Mode with EDO Mode"

Is it FPM with EDO? Wtf??? Either it is FPM or it is EDO.

What makes it confusing is assuming that "EDO" is supposed to be "an improved version" of "FPM", which implies that there should be a sort of fallback compatibility mode.

Which is all wrong and deceiving as the ram controller on the X terminal expects the data to "disappear" from the bus as soon as the CAS signal is released, while the EDO keeps it alive, confusing the older (1) MIPS ram controller.

That will cause "Bus Contention".

On YT, there's this video, suggesting the answer is No, it won't work unless you "mod" the hw.

(1) The EDO technology appeared in 1995, while the Xterminal is based on LSI LR33020, whose ram controller was designed in 1997 with a conservative approach, therefore based on 1994 technology.

[DiTBho]

Meanwhile, I took the risk of buying the ram kit.

[SiliconWizard]

I haven't dealt with FPM/EDO RAM in ages so I don't really remember the details. Well, last time I used EDO RAM was to upgrade a LeCroy scope a few years ago, but the manuals were clear about the type of RAM supported.

Now after reading some, it looks like EDO RAM should be backward-compatible with FPM and will run in FPM mode if the machine only supports that (hence the "EDO mode"), so that should work. Hopefully.

[ejeffrey]

A lot of doubts about the FPM_with_EDO_mode to FPM backward compatibility

Anyway, thanks to a VPN, I found the datasheet.

I thought that EDO memory was compatible with FPM controllers, it just didn't work any faster?  My memory is certainly hazy that far back, but I remember that EDO quickly became universal in the marketplace and it was common to upgrade older systems with EDO to run e.g., Win95.

[Zoli]

A lot of doubts about the FPM_with_EDO_mode to FPM backward compatibility

Anyway, thanks to a VPN, I found the datasheet.

I thought that EDO memory was compatible with FPM controllers, it just didn't work any faster?  My memory is certainly hazy that far back, but I remember that EDO quickly became universal in the marketplace and it was common to upgrade older systems with EDO to run e.g., Win95.

AFAIK, is the other way around: EDO controllers accepted FPM. One example is the aforementioned HP Laserjet 4, which accepts only FPM, no EDO. I vaguely recall a motherboard(Intel chipset socket 7, pre-MMX) where you had option between FPM(default) or EDO in the BIOS. With EDO SIMMs, it worked in both settings; with FPM SIMMs set to EDO->CMOS reset to clean up.

[DiTBho]

The ram controller on the X terminal expects the data to "disappear" from the bus as soon as the CAS signal is released, while the EDO keeps it alive, confusing the older (1) MIPS ram controller.

That will cause "Bus Contention".

This is the problem

[Zoli]

Meantime, I've dig out the SIMM's: 70ns HY514400(A), so it's a no-go.

[DiTBho]

[ejeffrey]

This is the problem

I'm confused and your diagram also looks like edo dram should work with a fpm controller.  I find both explanations online, but they don't make sense.

The CAS and RAS timings are generated by the controller.  So an FPM controller will always use FPM timings.  An EDO controller performing a read burst is allowed to start the next CAS cycle before it has completed latching the data because it's guaranteed to stay valid for longer.

But in your FPM timing diagram that's just the empty space between "valid" blocks.  An FPM controller using FPM timings shouldn't care what's on the bus at that time, it's invalid.  And it won't signal a new CAS cycle too early because it thinks its using the FPM timings?  Or am I completely misunderstanding?

Is the issue with multiple modules interleaved?  That the data hold of one module interferes with the data phase of the next module

Obviously an EDO controller that tried to use EDO timing would fail on non-EDO memory, they would need an option to turn EDO mode off.  IIRC this was all before dram modules had SPD chips, so you needed to program timings in the bios.

[DiTBho]

Is the issue with multiple modules interleaved?  That the data hold of one module interferes with the data phase of the next module

Precisely.

On the Tek xp400, the ram bus is 64bit, there are four sim modules.

Slot0, Slot2
Slot1, Slot3

Two Slots are always paired.

Bank0: Slot0, Slot2
Bank1: Slot1, Slot3

Slot0,Slot2 are first class, the other two Slot1,Slot3 are "optional"; if you install them, then the ram controller will interleave A-B.

So, you should somehow force high impedance between two cycles to fix the interleaving problem, because EDO doesn't automatically release the bus.

No high impedance.

[DiTBho]

I analyzed the timing, again.

A controller born for FPM sends the "End of Read" signal and expects the data to disappear from the bus within 10ns.
But each EDO module holds it there for 20ns.

So, even without interleaving, you may still get corruption if the controller tries to write immediately after reading.

Out of 10ns!!!

[DiTBho]

Meanwhile, I ordered qty=4 FPM modules, 60ns.
So I will be able to "check" and "test" these hypotheses.