MC6850 trouble

[Wawavoun]

Hi All,

I have a serial interface for a home build Flex computer made with a MC68B50.

This chip need a bus timing sync clock named E and a separate rx-tx clock.

The rx-tx clock can be provided by an output of a 6522 via (CB1). In this case I use a clock at 153600 Hz and a 16 divider in the the acia giving a 9600 baud transmission.
In this case everything works well.

I can also use the E (bus timing sync) signal as rx-tx clock. This signal run at 1843,2 KHz. Using the same divider this should give a 115200 baud transmission. This did not work.

I have already use this specific MC68B50 at this transmission speed (1843.2 KHz rx-tx clock and 16 divider) but with a higher E frequency (2 MHz).

I cant see where is the problem except that using the same clock for both functions is problematic but I dont find anything on this point into the datasheet.

Any opinions and may be solutions ?

Thanks and regards.
Philippe

[iMo]

Is the E signal aprox 50% duty cycle?

[Wawavoun]

Yes.
This signal is made by a 6809 processor clocked at 3686.4 KHZ and go to the bus through a 74LS244 (in fact from cpu to bus Q become E and E become Q because the LS244).

[Wawavoun]

Well.... Crystal frequency is 4xE so E is not 1843.2 KHz but 921.6 KHz --> 57600 baud.   

Problem solved !

Thanks to those that try to help.

[DiTBho]

Crystal frequency is 4xE so E is not 1843.2 KHz but 921.6 KHz --> 57600 baud.   

I also made this mistake, think that I had not only read but also highlighted with a yellow underliner the note in the datasheet where it clearly says 4xE, but then, resuming the project between one weekend and the next, I forgot about it

(in this... I can say that compared to paper notes, taking notes on Remarkable2 helps a lot)

so ... to fix the problem without re-desiging the whole PCB, I had to decouple the UART from the CPU and built a "baud-generator" circuit dedicated to its UART.
It uses a counter coupled with a digital oscillator. I have jumpers to select the desired bps.

- - -

Another note: I have developed several asynchronous serial lines in VHDL, and I must tell you that the RX part is much more incline to decode a bit incorrectly than the TX part, and to make it a little more robust I use 2x clock in order to sample the signal more stable.

This way I avoid more bits incorrectly detected, and I can measure it in terms of error rate on long continuous transmissions, where I evaluate the CRC, which is good, but.... it costs 2X clock oversampling.

If this trick is used in ASCI chips, it means that the TX part can be overclocked much more stably than the RX part