Hello!
I'm a 1st year Masters student at Polytech Paris-Saclay (France) and I'm looking for an internship opportunity in Australia, from May to August 2020 (3 months). I'd prefer to be based in Sydney, but I'm open to other places.
I'd would like to work on HDL design or verification. I do VHDL and Migen/nMigen but I'm not afraid of Verilog or other HDL languages. I also have good skills in embedded C/C++ (bare metal, RTOS and Linux) and in reverse engineering.
Send me a PM for further details or to get my CV. My WHV visa is ready ;-)