80C51 dev. board design

[ealex]

Hello

I've started developing a board for a bunch of 80C552 chips I had laying around.
The design is based around Philips PCB80C552-5-16WP chips in PLCC case

It is based on the schematics from PJRC ( http://www.pjrc.com/tech/8051/ ) and  Wichit Sirichote ( http://chaokhun.kmitl.ac.th/~kswichit%C2%A0/8051sbc/8051sbc.html )

The memory space is designed as:

Range	Data read	Data write	Instruction read
0x0000 - 0x7FFF	Peripherals	Peripherals	EPROM / EEPROM
0x7FFF - 0xFFFF	RAM	RAM	RAM

The EPROM socket is designed to work with UV erasable EPROMs(M24C256) and with EEPROMs. The selection is made with some resistors that need to be installed in different configuration for each type ( R1, R2, R3, R4 of page 4 of the attached PDF ).
I intend to use an 32kB windowed EPROM in the final version and and EEPROM during development.

The signals to external peripherals are wired to an 40 pin connector that also provides 5V and unregulated input power ( I can use already available IDE headers and cables ).
The peripheral bus consists of A14-A0 address lines, D7-D0 data lines, RD, RW and OE signals generated from the address decoder ( page 1 ).
The peripheral A14-A0 lines are tri-stated when there is no peripheral access by U4 and U5 hardwired as output-only ( pin 1 connected to logic '1' , page 2 ). The peripheral data bus is also floating in normal mode, but the direction is controlled by the RD signal.

The power supply consists of a simple 5V 2A buck regulator with a series protection diode on the input ( page 3 ).

All unused pins of the CPU are available on external headers ( page 5).

sbc_board.pdf contain fabrication output (first iteration). I've tried to keep it as small as possible.

This is my first time designing a system from scratch and using 80C51. Is there something obvious that I missed ?


Thanks,
Alex

[nctnico]

I'd use 74xx138 and 74xx139 as address decoders. Another thing to watch out for is disabling the address decoding when ALE is active. On some 8051 devices you can have glitches on RD or WR which lead to memory corruption.

[free_electron]

a couple of problems

technical :
- put a diode antiparallel with the rest capacitor.(c14)
- put a reset switch on the board (short cap)
- the 1000 uf capacitor after the switcher is way too large.
- put  proper reference generator for the adc convertors. something like a 2.048 or 4.096 volt reference. gives you nice numbers without having to resort to floating point calculation
- get rid of that stupid 373 and replace it with a 573. makes routing easier. (u9) i dont understand why people keep messing with these staggered pin chips. 373 -> 573  374 -> 574
- there should be a bulk capacitor BEFORE the switcher. 220uf or 470uf.
- put a max 232 and db9 connectoron the board. if you are smart you will even ditch the max232 double the circuit and also install an ftdi232h wired up to the rs 232 pins...
- make your 28c64 a 29c256 instead. flash and you can make a bootlaoder that can reflash in circuit. remembor on a 8051 you have access to the full 64 K of ROM and the full 64k of ram giving a total of 128 K memory ! don't limit yourself !
- i would partition as follows :
- 32k ram 0 - 7FFFF
- 8K EEprom 8000 - 9FFF
- A000 -> above : IO space
- 32K flash user rom 0 - 7FFF
-  add a dedicated IO circuit like a 8255 at A000. wire up an LCD display to one of its i/o ports. use the other two ports as general purpose I/O. you can have one with an ULN2803 installed as high current output and one with a 330 ohm series network and 10K pullup as dedicated input.
- put 330 ohm series resistors on all the IO pins of the 82522. that way you cant blow up anything if you make a short on the connectors.
- the 80522 has an i2c bus... find the two pins and slap on a 24C32 , a PCF8583 RTc with battery backup. those come in handy very often...
- you are bringin out the addres and databus to a connector : please dicht the 245's ... use 540 or 541 as address drivers.
- make a paging decoder with a 74138 as already suggested. it's much easier.

Graphical comments:
- clean up your schematic. overlayong ports on wires is just not done ... it's ugly and problematic.
- switch your sheet size to 11x17 or A3.
- wire your ram and rom using buses and bus entries. ports are not supposed to be used for on-page connections. ports are for hierarchical connections. use nets and bus entries for on page connections

pcb layout comments
your board is large enough to hold all the stuff i mentioned.
your routing is pretty clean
your holes for the plcc socket are WAAAAy too large.

[free_electron]

computers don't have serial ports anymore. hook up the TXD and RXD to a max232H and put a usb connector on the board. it will make your life easier.

the address bus is unidirectional . no need for a bidirectional bus translator. a 541 is unidirectional  ( 540 is an inverting version) the advantage is you have two OE control pins so you save an OR gate in your adress decoder.

[Alana]

When i was playing around with this subject in technical highschool we had GAL16v8 in our classes program and i used this chip as adress decoder. Saved me some trouble with adress decoder - one IC instead of many. And this was fun because i had to do it manually - our school havent had any compilers for GALs just simple programmer.

And one more trick from the old days - i used 2 precision DIP sockets soldered together to make converter from 27C256 UV erasable EPROM to 28c256 EEPROM i used in development. Usefull stuff if your board doesnt have those extra jumper resistors. Schematic of this part is identical

For ditching MAX232 - have you seen RS232 on modern computers, especially laptops? I have not - this is why its suggested to integrate USB to RS232 onboard but out of FTDI chip you would have TTL levels anyway.

[ealex]

wow ... thanks
a lot of info
I will not add a RS232 converter - i have some FTDI usb modules that i've done for another project.

free_electron:
"- put a diode antiparallel with the rest capacitor.(c14)" - ok
"- put a reset switch on the board (short cap)" - P1 on page 5
"- the 1000 uf capacitor after the switcher is way too large." - i'll reduce it to ~ 220u
"- put  proper reference generator for adc " - i don't intend to normally use the ADC - that's why it's directly wired to a header . the chip will be ok if AVREF+ is floating ?
"- get rid of that stupid 373 and replace it with a 573." - will do that
"there should be a bulk capacitor BEFORE the switcher. 220uf or 470uf." - C25 and C26 now - way too large from what you say, i will drop them to 470uF. I tend to choose values way too big, not economical but "safe" ....
"- put a max 232 and db9 connectoron" - no, i have some FTDI based modules
"- make your 28c64 a 29c256 instead ..." - there is room for a 32k PROM / EEPROM. i'll think of updating the ROM on board.
regarding the address space - i think i'll leave it as it is now - I want to have all 15 address bits for the peripheral bus
the same for the IO circuit and LCD - i'll add them as an extra  board.
"- put 330 ohm series resistors" - will add
"please dicht the 245's ... use 540 or 541" - why ? what is their advantage ?
the I2C bus is sent to one of the headers.

Regarding schematic comments :
i'll remove the ports and add busses and bus connector ( for some reason i hate them and never learned to use them properly )

Alana:
i've seen GAL16v8  used on some other projects but i don't have one around
"2 precision DIP sockets soldered together to make converter from 27C256 UV erasable EPROM to 28c256" - nice idea

nctnico
"disabling the address decoding when ALE is active ...  " - i'll think about it.

[westfw]

Is there a modern equivalent of 8255?  It seems like such an ancient chip, but they're still so common on 8051 boards...
(heh.  A modern microcontroller (say, an AVR) ought to be about fast enough to emulate an 8255 in software, if you're looking at a ~12MHz 8051.  Probably not quite fast enough to do the version with the built-in address latches, though.)

[JoeO]

You might want to think about adding screw holes to the board to mount it in a chassis.

[ealex]

82c55 - just for the fun of designing a system with it ( too much free time ) and using some parts that just sit around - i know it's very slow, etc.
for the PLCC socket pins - 0.8mm holed with 1.2mm pads will be enough ? now I have 1 with 1.6mm

[free_electron]

free_electron:
"- put a reset switch on the board (short cap)" - P1 on page 5

that don't look like a switch to me ...

go download my altium library...

"- the 1000 uf capacitor after the switcher is way too large." - i'll reduce it to ~ 220u

no, you need to look up in the switchers datasheet whow to calculate the correct capacitance. switchers don;t like itif you just slap on capacitor values that are ten or hundreds of times too large.

"- put  proper reference generator for adc " - i don't intend to normally use the ADC - that's why it's directly wired to a header . the chip will be ok if AVREF+ is floating ?

no. avref+ can't be left floating. it needs a supply.

regarding the address space - i think i'll leave it as it is now - I want to have all 15 address bits for the peripheral bus

seems like you dont grasp the concept of address decoding and partitioning. or how the adressing on an 8051 works

8051 has 4 memory spaces
- SFR's special function registers. these are internal in the chip , serial ports, adc , timers etc
-IRAM internal ram. very limited 128 or 256 bytes of ram
-XRAM external ram : 64Kbyte address space
-ROM either internal or external dictated by the state of the EA pin : 64K address range.

it does not make sense to bring out the ROM space on the expansion connector. Rom is on board. put two chip sockets if you need to. ROM space is always READ ONLY. there are no instructions int he 8051 that can write there.

The PSEN pin selects between XRAM and ROM space (Program Store enable)
normally you wire up 27c256 eeprom's as follows : : wire them into A0 to A14
A15 gets an inverter. A15 OR PSEN goes to CE of first rom , A15\ or PSEN goes to PSEN of the second rom
the RD\ pin controls the OE\ of the eproms

you will have no glitches if you do it this way. this is the only correct bus cycle. anything else is a kludge made by people that dont understand the 8051 bus cycles.

Rams and any io circuitry are only active if PSEN is high
so you use PSEN to control the active high enableof an 74138.
Wire your 32K ram into the lower address range ( NAND the lower 4 outputs of the 74138 ) and control the CE pin
RD pin goes to OE WR pin goes to WR of the ram.
the upper 4 outputs of the 74138 become expansion selects.
bring out tha address bus , databus , rd wr and those select signals anfd off you go.
your IO connector is now properly partitioned and no matter what gets connected externally cannot interfere with the hardware on themotherboard as the decoder blocks that off.



My other remarks were because your board is so large and vempty. there is plenty of room to put on the eeprom and rtc chip , ftdi chip and some other stuff

Send me the Schdoc's and pcbdoc and pcbprj. I'll tweak it a bit and show you how to draw  proper schematic and do the memory decoding of the 8051.

Some people suggested using a PAL or GAL for the decoding. stay away from that. while those are great they are an additional problem to deal with. you need a pal programmer, the software to make the fusemap and if you have never done that it is more trouble than it is worth. the glue logic needed is only aninverter a couple of or gates and a nand and a 74138 ( you may even get away without the 74138 ...)

[Carrington]

Ealex please, listen to "free_electron" because he is one of the wise men at this forum.

[nctnico]

8051 has 4 memory spaces
- SFR's special function registers. these are internal in the chip , serial ports, adc , timers etc
-IRAM internal ram. very limited 128 or 256 bytes of ram
-XRAM external ram : 64Kbyte address space
-ROM either internal or external dictated by the state of the EA pin : 64K address range.

Actually 3 areas. SFRs and IRAM are in a shared area where you can't use all of the 256 bytes of RAM.

And really make sure to use the ALE signal as well on the address decoding of the RAM. Just regard RD and WR as undetermined when ALE is 1. I vividly recall a company needing to replace devices all over the world because a designer cut a corner (fortunately it wasn't me  ).

[westfw]

Just regard RD and WR as undetermined when ALE is 1.

Really?  Damn.
I've been fiddling with an 8051 design that uses a 64k RAM chip that I just left selected all the time (and it doesn't use/need any decoding.)  That doesn't work eh?    But I could just tie one of the CS/ signals to ALE and get by?  (I think that will wreck the lovely single-sided PCB, though.)

[free_electron]

That ALE story is bogus. Ale is only used to latch the address from the muxed address data bus.
None of the intel schematics use it for any other purpose.

[calexanian]

Making me all nostalgic for the bundle o tubes I have of 8049's that never had the internal rom masked for us. I know its not an 8051 but..... Many of those systems of ours are still in use out there in water filtration stations on farms all over, 20 years after we stopped making them.

[ealex]

free_electron, thanks again.
i'm just starting to realise how much i don't know 

The idea of using 2 ROMS is great.
I've messed up the board while working with busses and linking them between different pages, but after reading the documentation i think i got the hang of it - at least how to make them work properly.

Updates:
 - added reset switch
 - added 4.096V AVref supply
 - decoder as described by free_electron, without using the 74138 - extra decoding will be done for each peripheral
 - added resistors for all output ports
 - added second 32k ROM
 - added i2c eeprom and RTC, just symbols, no footprint yet

Next:
 - update the schematics after free_electron will correct my mistakes
 - finish schematic for i2c eeprom / rtc
 - redesign the PCB - shrink it as much as possible

Questions:
 - how should I proceed if I want to be able to update eeprom 2 in system ( the one from 0x7FFF ) in my schematic ? - my idea is to link #ROM_CE2 to #PER_CE when I want to write to it ( removing all peripherals ). eeprom 1 (0x0000 - 0x7FFF ) will have the bootloader
 - can i simulate an EEPROM using a 32K sram with a battery ? - just during development

thanks

[free_electron]

 I'll "massage" the schematic over the weekend.
Ive done a number of boards with all kinds of 8051 in my lifetime...
8051,8052,80152,80154, 80552,80537,80652,80c752,80c751,80c2051,89c54 almost all of the silabs beasts i cluding the F100 and F120 and ive place the oregano systems core in several FPGA's.
Ive also done the 8052 ah basic. I even have the source for that thing. I also have all of the original intel compilers (assembler, pl/m and c).
It is very easy to make your design compatible with the intel basic. I'll see if i can find the adapted binary for the 552. It does exist.

[nctnico]

That ALE story is bogus. Ale is only used to latch the address from the muxed address data bus.
None of the intel schematics use it for any other purpose.

Then the intel schematics are wrong. I've seen the glitches with my own eyes! Nowadays memory is so fast that it even sees a small glitch as a valid write signal. You are free to discard hard learned lessons though.

[free_electron]

The RD and WR can glitch all they want. if CS is not active on the memories nothing will happen. Bus timing gives that RD and WR only become valid one or even two internal cycle after deassertion of ALE.
If you mess up the address decoder so that the propagation delay in the decoder is longer than the cycle (1/12 of the clock in a standard 8051 , 1/4 or 1/2 of the clock in either a Turbo 8051 core or a pipelined 8051 core like the F100 from Silabs) Then and only then will you see this problem.

A standard 8051 is clocked at 12Mhz. you have 1 microsecond between ALE de-assertion and RD or WR activation. if you mess up the decoder to have 1uS propagation delay you shouldn't be designing digital circuits. Do the same with a Turbo core clocked at 40Mhz and 2 clock per cycle and you are now in the 20 to 40 nS range.. with classic TTL that can be f-ed up very easily... you will need F series as HCT and Ls won't cope with that anymore, they conk out at 20 to 25 MHz.

I'm not arguing that there aren't any glitches possible during the ALE cycle ( although i have never seen em), i'm saying that, if the decoder meets the setup and hold times it will not be a problem. Anyway ,as ALE is asserted the address latch transitions state as well.

Most likely those glitches were seen with something like a Temic 89c51 or a Siemens C500 or C510 chip. Those are the Turbo cores with reduced instruction cycles. If that designer made the decoder using the data for a standard 12 cycle implementation like the 8031 8032 or the 80552 like the TS is doing , and you plopped in a turbo core alternate you can bet top dollar you will get burned. But then that guy is an idiot , as he should have checked the relevant documents and made sure the decoder met set up and hold times. Too many times people make a circuit using a datasheet from a different vendor. ' But they are both 8051's ?.. sure. The only relation between your grandma and my grandma is that they are both grandparents. that's where any similarity ends...

There is a reason that stuff is documented. Violate it and bear the consequences.

None of the intel example schematic ( again : INTEL original 12 cycle core ) show usage of the ALE signal for anything else than the address latch. I have the original intel application handbook for the 8051 ( 600 page clunker ). I can't speak for the turbo cores, i know they exist, never used them. The silabs don't have the potential problem as they have all the memory you could possibly want on board.

[westfw]

The RD and WR can glitch all they want. if CS is not active on the memories nothing will happen.

Hmm.  But I was just going to leave CS active on my 64k memory.  Always.  OE to (PSEN+RD), WE to WR, overlapping data and program memory (allowing bootloaders) occupying the full address space (no decoding necessary.)  An unusually memory-rich and IO poor implementation of an 8051 experiment board...

The address decoder is always going to be selecting something on a fully decoded system; if there are ever glitches on RD or WR, isn't that going to be a problem?  ALE isn't usually included as part of the decode, is it? (CS = f(addr), not CS=f(addr, ALE))  The only other choice would be CS = f(addr, RD, WR), but if RD and WR are where the glitches are, that wouldn't help...

And... Turbo cores don't default to regular-core compatible external memory timing?  Rats.

[lapm]

free_electron, thanks again.
i'm just starting to realise how much i don't know 

Now that my friends is beginning of wisdom. Realizing you don't really know much yet.

[SeanB]

I have seen ALE used as a part of the decode logic and it not used as all, really depends on the speed of the device and the decode logic. If you are using a 8MHz part with ls logic you can use it, but it adds extra logic gate delays. If you use really fast logic decode then you can run the device at a higher speed or use a high speed core. Always RTFM for the decode logic, the major reason most went to a PLD decoder was not the complexity of the logic but the much reduced delay of the decodes, allowing you to use a slower cheaper RAM and ROM while still having enough margin for the chip to fetch and deliver data to the external memory or IO.

[westfw]

Always RTFM for the decode logic

The problem is that if you're dealing with "mostly legacy" chips like an 80552 or original-speed 8052 of some kind (anything in a DIP40?), then "the manual" tends to be mired in ancient logic families and obsolete memory chips.  ("Your 74138 decoder chip will allow you to select one of 8 8k 200ns 27c64 EPROMs or 8k RAM chips."  Right.  No thank you.)

To me, one of the things that makes an 8051 still "interesting" is the possibility of large external RAM memories.
That, and the "stock" of chips I have sitting around :-(
Otherwise I'd just go and buy a $100 dev kit from silicon labs...


To the original poster: make sure the plcc socket you're using is the same as the sorts of plcc sockets that are still available.  An near-unobtainable variety of socket that costs more than a modern MCU chip would be frustrating!  (also, consider a version that mounts the 80552 direct to the board.  "modern" sockets tend to use the same footprint as the actual chip.)

[free_electron]

i did some tinkering over the weekend.
i'll massage it a bit more this week and then post the entire design files

[ealex]

i'm back.
westfw - i also have the plcc sockets ( received the cpu's and sockets and a bunch of eeproms )
free_electron thanks again, meanwhile i've started reading about SDCC compiler for 80C51 and preparing a toolchain and an emulator to have something working until I get the pcb manufactured.