On/Off Circuit Unstable Issue

[GeorgeIoak]

I found a reference design for an ON/OFF circuit mainly used for the Raspberry Pi, located here and here

I was designing another board and inserted this design into my board which I believe is identical except for the MOSFETs used and 340k instead of 300k resistors. My schematic is this:



My current testing is with this circuit not connected to anything other than the incoming power rail (5V2, No H3 header and nothing connected to Pi_GPIO20 or Pi_GPIO21).

With nothing connected this circuit is supposed to be OFF (Q2B P-FET OFF) but most of the time the circuit is ON and I get voltage at Pi_5V2 (nothing connected here either).

In the attached document I have some scope plots and information. To be honest, I understand the circuit but I'm a little confused on the operation so I thought it's time for a refresher course and there's no better place than to come to this forum.

Your help in breaking down this circuit and finding what needs to be changed would be greatly appreciated.

Thanks in advance,
George

[Wimberleytech]

If you really have the source/bulk of Q2A connected as shown (but your transistor drawing is wrong BTW) then there is a parasitic diode with anode at the gate of Q2B and cathode to ground, pulling the gate of Q2B down to turn it on.

If you have Q2A connected properly with the source/bulk connected to ground, then the gate of Q2A is tied to 5V via inductor FB2 and thus will be on, pulling the gate of Q2B to ground and turning it on.

The circuit you are trying to implement (based on the examples you cite) are designed for a ground-referenced load.  You are trying to use it with a high-side load.  Not the right circuit for that.

[GeorgeIoak]

My mistake, I thought I had corrected the symbols before I posted. The symbols were drawn wrong when I created the SI5515 component but the actual footprint and connections match the reference design (source of Q@a is grounded and source of Q2B is connected to 5V2).

5V2 is the input to the circuit and Pi_5V2 is the output. My application is the same as the reference designs (applying and removing power to the Raspberry Pi) and the P-FET is used on the high side which seems correct to me, why do you say that it's not?

[Wimberleytech]

Put a 1K resistor from Pi_5V2 to ground and try again.

[GeorgeIoak]

OK, that seemed to do the trick. I'll need to do some more testing but at least 3 or 4 times powering it up it started with nothing on the output (Pi_5V2). I shorted H3 briefly and that turned it on.

Thank you but could you know help me better understand this circuit and what's going on. Specifically I have these questions:

• Why is D5 connected back to the source of Q3?
• Is R44/R46 used as a voltage divider for the source of Q3 (when Q2A is ON). Since the Pi has 3.3V GPIO won't Q3 always be OFF and cannot be turned ON?
• How is C23/R45/C22 connections work?

Thanks again!

[Wimberleytech]

The 5515 transistors do not appear to have intrinsic gate protection (best I can tell from the datasheet), so my guess is that the diodes provide protection from potential electrical overstress.

Re R44/46 not really voltage dividing (at dc at least) because the mosfet has infinite input resistance (for practical purposes here).  I think the designer wanted an RC delay driving the gate of Q2A (this the 340k) but did not want to short Pi_5V2 to ground (thus the 100k).

Re C23 R45 C22, this design is for a momentary switch.  Q2a/b have positive feedback, so to switch their state, all you need to do is pulse the gate of Q2B negative.  That is accomplished with the differentiator C23 R45.  C22 may not be necessary but there to deal with any interference.

[Wimberleytech]

Oh, C22 is there so that when power is applied to 5V2, the charge on C22 is zero, so Q2B does not turn on by default.  Requires a momentary switch operation to turn on.

[GeorgeIoak]

OK, so I'm getting a better understanding of this now, thanks. What about Q3, when Pi_5V2 is "ON" it's source will be at 5.2V and the gate is either pulled to 0V by R47 or Pi_GPIO21 is 3.3V when driven high. Both of those conditions should turn Q3 ON. That pulls the R44/R46 junction to 0V, right?

What about turning Q3 OFF? Does that only happen when the switch is pressed which causes the source (R44/R46 junction) to go to 0V?

[Wimberleytech]

Q3 is a source follower and thus it is always on and the source is one threshold above the gate.  The threshold voltage is 0.5 <|vth| < 0.9.  So, when GPIO21 is at 3.3 volts, Q3 source is at 3.8 to 4.2 volts.  Either of those voltages is sufficient to turn on Q2A.

When GPIO2 is at ground (0 volts), the source of Q3 is between 0.5 and 0.9 volts.  The threshold voltage of Q2a is: 0.4 < vth < 1.0.  If |vth| ov Q3 is high and vth of Q2a is low, Q2a still turns on. 

Not sure what the purpose of GPIO21 is anyway.  To turn off power, the idea is to hold the switch on until the gate of Q2A decays, turning off Q2A

[GeorgeIoak]

Do you think I chose Q3 with too low of a threshold voltage?

[Wimberleytech]

You NEED a low threshold voltage for Q3.  Needs to be lower than the threshold voltage for Q2A

[GeorgeIoak]

Well that could be 1 issue:

• Q2 Dual MOSFET used is a Vishay SI5515CDC-T1-E3
•    Vgs of N-FET is minimum of 0.4V
•    Vgs of P-FET is minimum of –0.4V

• Q3 P-FET is a Diodes Inc. DMG2305UX-7
•    Vgs is minimum of –0.5V

[GeorgeIoak]

I had some time to get back on this project. I'm using the MOSFETs described in the post and haven't had a chance to change them but I wanted to ask a question.

I've configured the Pi and with this circuit the following happens

• On initial power everything is OFF which is the correct operation
• A push of the power applies power to the Pi which boots up
• If I hold the power button for more than 3 seconds the power is completely cut off (as expected)
• When the Pi powers up GPIO21 goes high and when the shutdown command is issued GPIO21 goes low

From my understanding when GPIO21 goes low the power should be cut off after ~3 seconds but this isn't happening.

Is this because my Vgs for Q3 is higher than the Vgs for Q2?

In the reference design their dual MOSFET is the Vishay Si4562DY which has Vgs of 0.6V (min) and 1.6V (max) for both the PFET and NFET.
They use a SI2301 PFET (Q3 in my circuit) which has a Vgs of -0.45V

[Wimberleytech]

Yes, that is why.

[GeorgeIoak]

Since I used the Vishay SI5515CDC-T1-E3 for the dual FET and it has Vgs of 0.4V it was difficult to find a PFET with a lower Vgs so I ordered a different dual FET, the SI5504BDC which has a Vgs of 1.5V.

I should be getting those in later today and I'll report back after I replace and test with hopefully good news and a closure on this thread!

[GeorgeIoak]

I got the new dual FET  in and replaced Q2 and the first power up and down worked perfectly. When I tried it again though the board would power on and then power off. Since the gate of Q3 needs to go high early on I set the scope to trigger on Pi_3V3 and see how long before GPIO21 went high. From the attached scope plot you can see it takes right about 4 seconds which I think is just beyond the window of this circuit. I need to look into why GPIO21 is taking so long to go high but in case I can't reduce that time do I just need to increase C24's to hold the power on longer?

[GeorgeIoak]

One other thing about this circuit that bothers me is the pull-down on the gate of Q3 (P-FET that gets a low signal from the board when system shuts down). Why do you want the default state of this FET to be ON?

[Wimberleytech]

When the system shuts down, there is an unknown output at an I/O pin.  Thus the resistor is there to insure that Q3 gate is at ground.

[Wimberleytech]

Why do you want the default state of this FET to be ON?

I dont understand your question.  What do you define as the "default state?"

[GeorgeIoak]

Default state meant to be when the gate isn't driven by GPIO21. I understand that you normally have a pull up or down on a gate so you don't have an unknown condition but in this case I'm curious why it's defaulted to turning the FET ON instead of OFF.

[Wimberleytech]

Short answer: It is how the designer thought best to solve the need.

Once Q3 turns on and pulls the gate ov Q2A low to turn it off, Q2B shuts off and there is no power delivered to Pi_5V2 so all of the boltages on R44, R46 Q2A_gate, Q3_drain collapse to ground eventually (once Q3 returns to accumulation, the reverse biased diode will leak the rest of the way to ground).

So, Q3 is approximately off once the power to Pi)5V2 goes away.

[GeorgeIoak]

I guess the operation of Q3 is what is causing my brain to bend a little. The only time it is OFF is when Q2B is OFF which yields no voltage at Pi_5V@. Since the Pi is 3.3V you can never make the gate higher than Pi_5V2. Sorry if I'm being dumb but I'm missing a little light bulb moment I think

[Wimberleytech]

3.3V is high enough. 3.3+Vt(Q3) > Vt(Q2A)  ==> Q2A is on, power is delivered to the Pi.

Dont think about Q3 being on or off...just think about it controlling the gate of Q2A.  If it feels better for your brain, imagine that it is mysteriously always on and the voltage at the source is one Vt above the voltage at its gate.  Once you get comfortable with that, then recognize that the collapsing voltage on the source (when Q2B turns off) ultimately turns it off.