Report single pin nets on Heirarchical schematic

[tesla500]

When I use the report single pin nets tool on a hierarchical design, only the current schematic is reported, showing nets that go to other schematic levels as being single-pin when they're not. How do I get this tool to work?

Regards,
David

[thmjpr]

Can you explain what kind of hierarchical design (device sheets, sheet symbols)? Or maybe an example screenshot.

If I create a single pin net and connect that net on another schematic page, its ok.
Or if I connect to a sheet symbol, and connect the port to something, also ok.

Also, not sure if it helps but you should see the same info when doing a Project > Compile Project, and looking at error messages. Assuming you've flagged it under project options > error reporting.

[tesla500]

This is a hierarchical design using sheet symbols. Something like http://wiki.altium.com/download/attachments/3080261/sheet+symbols.png?version=1&modificationDate=1228187099001.

Thanks for the suggestion to check the setting in project options. That works properly for identifying single pin nets, but the Reports | Report single pin nets command doesn't work right, the report it generates appears to only look at the sheet I had open when I ran the command. The compilation error checking is fine though, I think I'll just use that.

Regards,
David

[maxseeley]

No, there is some other issue in the way the project is setup, in the project options, or in the way you are labeling your nets.  If you want me to take a look at it, please email your project file to me or post it if you are comfortable.  The reason are there are numerous things that could be causing this.