Author Topic: ESD Zeners in this diagram ?  (Read 3635 times)

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Offline kellogsTopic starter

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ESD Zeners in this diagram ?
« on: April 21, 2023, 03:47:18 pm »
Hi,

Does this dual zener pack do anything whatsoever in the diagram attached ?

This is an automotive design, I don't think they have to do with any of the specific transients. Maybe they are supposed to address ESD ?

Talking about the 2BZX84C6V8-DIO pack.
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #1 on: April 21, 2023, 03:53:31 pm »
Not much I would guess.  When the transistor blows up, D-G current just flows into the MCU anyway.

This isn't really a "design", there's no designators, right?  Right?

Tim
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #2 on: April 21, 2023, 04:01:10 pm »
When the transistor blows up ? Oh no, how to protect it? Or better asked, could that zener pack be part of some half-missing FET protection circuitry ?

This isn't really a "design", there's no designators, right?  Right?

Tim

:D
« Last Edit: April 21, 2023, 04:07:42 pm by kellogs »
 

Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #3 on: April 21, 2023, 05:25:15 pm »
Since the 2BZX84C6V8-DIO a dual 6.8V zener, it looks like all it would do is limit the voltage at the gate of the FET to +- 7.5V...
It won't protect the MCU from a FET failure, as mentioned by T3sl4co1l already.
You could add a 2nd resistor which would limit the current into the zener diode in the event of a D-G short in the FET. (attached) May need a slightly lower zener voltage and different resistor values than shown depending on the characteristics of the zener and how fast you want to switch the FET on/off:

 

Offline floobydust

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Re: ESD Zeners in this diagram ?
« Reply #4 on: April 21, 2023, 05:39:48 pm »
OP's circuit is out to lunch.
NX7002BKS dual mosfet already has the gate zeners built in. Expecting the part TSSOP6 at over 1.2A...  well that's going to smoke.
Single mosfet NX7002BK also has the gate zener built in.
 
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #5 on: April 21, 2023, 05:52:39 pm »
Oh dear... since I can't get hold of the guy who sketched this up I am going to assume he meant to use another FET. Maybe one that would not smoke at 1.2A and also did not have those built in Zeners (which btw look to me connected the same way as those in the dual package).

@Kim Got it, but why leaving out the second zener between pins 2 and 3 ? I was just thinking one of them protects against positive transients (diode between 1-3) and the other against negative transients (diode between 2-3)?
 

Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #6 on: April 21, 2023, 06:04:56 pm »
@Kim Got it, but why leaving out the second zener between pins 2 and 3 ? I was just thinking one of them protects against positive transients (diode between 1-3) and the other against negative transients (diode between 2-3)?

A single 6.8V zener will let the voltage swing between -0.7V and +6.8V...
ie: It'll clamp negative transients at -0.7V and positive transients at +6.8V

There is no reason the voltage would need to swing below ground in this design. The MCU's PB0 pin can't go below ground anyway. Hence I showed a single zener in my diagram. You could use the other one to protect another IO pin if needed.

 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #7 on: April 21, 2023, 06:08:29 pm »
The other thing is it's a dummy load on +12V.  Maybe that's intended, who knows.

Maybe it was meant to be a 10k, and it's a logic output going somewhere else but there's no net label or wire, and it was just... left and forgotten?  It surely didn't pass any kind of design review, in any case.

I wouldn't think there's much meaning to be extracted from it.  Was it supposed to connect to something?  Was it an in-progress schematic that was dropped in the middle?  Was it all a hallucination, was it made by human hands (or by their intent) at all?  Who knows; probably doesn't matter much.

Tim
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #8 on: April 21, 2023, 06:40:17 pm »
@Kim Okay, but there area a number of FETs having two built-in zeners connected similarly to the diagram I have got. If only one is enough, why are they using two in series ?

Also, how would I go about preventing a D-G short in the first place ?

@Tim My load is a 12V lamp, so I guess he's just put 10 ohm in there for that reason...
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #9 on: April 21, 2023, 07:04:33 pm »
Oh it is a thing, alright.

...Wait, is *this* the design review?  Right now? 🤔

The usual way to avoid shorts is a suitable choice of MOSFET.  "Protected switch" types are popular in automotive application.  They offer modest peak current limiting, and transient and thermal limiting.

Tim
« Last Edit: April 21, 2023, 07:25:20 pm by T3sl4co1l »
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Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #10 on: April 21, 2023, 07:05:54 pm »
@Kim Okay, but there area a number of FETs having two built-in zeners connected similarly to the diagram I have got. If only one is enough, why are they using two in series ?

It allows for more flexibility. Those FETs can be used in many different products and in some cases being able to drive the gate negative is useful. But in your circuit that'll never happen. In fact, letting it swing -7.5V would be detrimental to protecting the MCU. Clamping it at -0.7V and limiting the current through the 4k7 resistor is much less stressful on the MCU's PB0 port than clamping it at -7.5V and letting much more current flow.
 
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #11 on: April 21, 2023, 08:24:40 pm »
Wait a minute. In a positive transient isn't the voltage regulator (will be of 5V variety) protected by  those didoes + resistor at entry  ? So that its ouptut will be at 5V and thus no more than 5V on FET's gate. So what good is the zener then ?
 

Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #12 on: April 21, 2023, 09:33:56 pm »
In the modified circuit I posted, the zener is only useful for protecting the MCU if the FET failed with a Drain to Gate short.
Yes, the regulator is somewhat protected by that diode, resistor, & zener on it's input. If the regulator's output spiked enough to damage the FET via the MCU, the MCU would have been dead already.
 

Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #13 on: April 21, 2023, 11:00:08 pm »
In that case I think the zener should be replaced with one that has a Vz lower than MCU pin absolute maximum = 5.5V. Not too low, so the FET gate won't get a lowered voltage in normal operation. Maybe a Vz = 4v7 or 5v1 will do fine.
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #14 on: April 21, 2023, 11:35:35 pm »
Just remove it -- it isn't doing anything in normal operation, and abnormal operation has other solutions.

Tim
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Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #15 on: April 21, 2023, 11:43:14 pm »
Just be aware that zeners tend to start conducting a little bit before their rated voltage. So while a 4v7 zener might be rated at 4.7V @ 60mA, it might start drawing 1mA when the voltage across it reaches 4.4V causing a voltage drop across the resistor and thus less voltage for the FET gate.
Also, most MCUs have protection diodes on most of their IO pins that will shunt excess voltage to the supply rails. The key is not to have too much current flow, which is the job of the 4k7 resistor between the IO pin and the zener. What MCU are you using?
ie: If you had a 6V zener, and the FET had failed, that would mean there would be 0.3V (6 - 0.7 - 5V) across the 4k7 meaning only 64uA of current would flow into the IO pin which wouldn't harm it.

I agree with T3sl4co1l... The zener isn't really necessary unless you are super paranoid or gonna blow up a lot of FETs while experimenting.
« Last Edit: April 21, 2023, 11:45:06 pm by Kim Christensen »
 

Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #16 on: April 22, 2023, 11:31:25 am »
This might be over my head, but I would like to learn how to protect that FET without a pre-packaged "protected switch". Maybe those 3 elements protecting the regulator can also be tweaked and made to protect the FET ?
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #17 on: April 22, 2023, 04:34:16 pm »
You need a whole lot more circuitry to do that. At least a shunt resistor to sense current (and perhaps limit short-circuit current as well), perhaps an op-amp, and some logic to handle the on-off behavior (perhaps an edge triggered flip-flop, and a timer to hold it off in fault mode).  You can't measure the die temperature with ~zero delay, as the integrated kind can, so you must either calculate SOA in real time (measuring voltage and current, and multiplying them) or use worst-case figures (say, measuring current but assuming maximum voltage, or measuring voltage and limiting current to a reliable value).  And that'll be relative to an assumed maximum ambient temperature, or you measure and incorporate that into the calculation.

Tim
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Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #18 on: April 22, 2023, 06:06:36 pm »
A low tech/effort way of protecting the FET would be to over spec the FET by a huge margin while also protecting it with a PTC fuse (current) and TVS (voltage).

Or you could just spend less money and use what T3sl4co1l suggested. For example, something like the NCV8403 might work for your application and it's going to be cheaper than DIYing or over spec-ing a part.
« Last Edit: April 22, 2023, 06:11:59 pm by Kim Christensen »
 
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #19 on: April 23, 2023, 05:20:25 pm »
How do these short circuits happen ? When the light bulb fails it wil fail open, no ?

Or it can be caused bymany other factors; maybe I should worry about it for not only the FET but the mcu and regulator also ?
 

Offline Kim Christensen

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Re: ESD Zeners in this diagram ?
« Reply #20 on: April 23, 2023, 08:08:56 pm »
Quote
How do these short circuits happen ? When the light bulb fails it wil fail open, no ?
Depends on the application... For example, if the bulb was a turn signal in a car, it's most likely fail mode would be going open... But then there's the scenario where the car has a fender bender and the lamp is smashed and gets shorted out. Or the user splices in a trailer plug and overloads the circuit.
You can't design for every crazy scenario and at some point you're going to have to accept a certain amount of risk. So what is this circuit to be used for anyway?



 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #21 on: April 23, 2023, 09:55:51 pm »
It could also be exposed to transients.  Likely not the full gamut of say ISO-7637, but a subset perhaps. 

Shorted or crossed wiring faults can also happen, whether due to aging wiring, or rodent damage, or water damage, or etc.  Or the worst scourge of all: aftermarket parts and too-clever-for-their-own-good end users / shade-tree mechanics.

If we're talking tungsten light bulbs, the startup current might well look damn close to a short circuit.  Again, something an oversized MOSFET can handle, but given some massaging of the SOA, a current-limited circuit might be cheaper (smaller die area).  Assuming the control circuitry is low cost, of course (which it can be, if integrated and purchased in the millions qty -- as protected switches are).

Tim
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Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #22 on: April 23, 2023, 10:59:56 pm »
Heh, I suppose as an example of protection circuits, this might be interesting:
https://www.eevblog.com/forum/projects/transistors-die-pictures/msg4829513/#msg4829513

Tim
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #23 on: April 25, 2023, 01:17:53 am »
I am looking to add extra lights on my offroader... an old soviet era creature that would look terrible with leds, so I would probably want to stick to good old tungsten. Dim them by PWM depending on lighting conditions. Or not, it would make matters more complicated. Drive instead a variable number of headlights based on surrounding luminosity.

Since there already is a MCU, maybe I can hook the current sense resistor to it, interrupt, then... then what ?

How about the fastest fuse I can get (at reasonable prices) ?
« Last Edit: April 25, 2023, 02:43:28 pm by kellogs »
 

Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #24 on: April 29, 2023, 04:57:48 pm »
"Protected switch" types are popular in automotive application.  They offer modest peak current limiting, and transient and thermal limiting.

Tim

Okay, point taken. So,

https://www.infineon.com/dgdl/Infineon-BTS7080-2EPA-DataSheet-v01_10-EN.pdf?fileId=5546d4625e763904015e941bf21e2dbe

They do not say it is good for negative transients but they do say it protects against reverse polarity. Until I get an answer from them (if ever):



Hello,

Looking into BTS7080-2EPA datasheet, i have got a question.

On page   7: "Power Supply Voltage VS -0.3 – 28 V "
On page 18: "Breakdown Voltage between GND and VS Pins in Reverse Battery -VS(REV) 16 – 30 V 1) IGND(REV) = 7 mA TJ = 150 °C"

I am not sure about "between GND and VS Pins" - since there is an R_GND on the diagram of 47 ohm recommended value, that would make the GND pin at roughly -0.33 V in a reversed battery situation. Do i understand well that the VS pin can actually withstand at least -16.33 V ?
If so, then will a properly designed diode clamp at less than |-16.33| V make the chip survive ISO type of negative transients  ?

Thank you



Attached the datasheet diagram for this device as well as what my diode clamp would look like.
 


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