Author Topic: ESD Zeners in this diagram ?  (Read 3675 times)

0 Members and 1 Guest are viewing this topic.

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
ESD Zeners in this diagram ?
« on: April 21, 2023, 03:47:18 pm »
Hi,

Does this dual zener pack do anything whatsoever in the diagram attached ?

This is an automotive design, I don't think they have to do with any of the specific transients. Maybe they are supposed to address ESD ?

Talking about the 2BZX84C6V8-DIO pack.
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #1 on: April 21, 2023, 03:53:31 pm »
Not much I would guess.  When the transistor blows up, D-G current just flows into the MCU anyway.

This isn't really a "design", there's no designators, right?  Right?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #2 on: April 21, 2023, 04:01:10 pm »
When the transistor blows up ? Oh no, how to protect it? Or better asked, could that zener pack be part of some half-missing FET protection circuitry ?

This isn't really a "design", there's no designators, right?  Right?

Tim

:D
« Last Edit: April 21, 2023, 04:07:42 pm by kellogs »
 

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #3 on: April 21, 2023, 05:25:15 pm »
Since the 2BZX84C6V8-DIO a dual 6.8V zener, it looks like all it would do is limit the voltage at the gate of the FET to +- 7.5V...
It won't protect the MCU from a FET failure, as mentioned by T3sl4co1l already.
You could add a 2nd resistor which would limit the current into the zener diode in the event of a D-G short in the FET. (attached) May need a slightly lower zener voltage and different resistor values than shown depending on the characteristics of the zener and how fast you want to switch the FET on/off:

 

Online floobydust

  • Super Contributor
  • ***
  • Posts: 7116
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #4 on: April 21, 2023, 05:39:48 pm »
OP's circuit is out to lunch.
NX7002BKS dual mosfet already has the gate zeners built in. Expecting the part TSSOP6 at over 1.2A...  well that's going to smoke.
Single mosfet NX7002BK also has the gate zener built in.
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #5 on: April 21, 2023, 05:52:39 pm »
Oh dear... since I can't get hold of the guy who sketched this up I am going to assume he meant to use another FET. Maybe one that would not smoke at 1.2A and also did not have those built in Zeners (which btw look to me connected the same way as those in the dual package).

@Kim Got it, but why leaving out the second zener between pins 2 and 3 ? I was just thinking one of them protects against positive transients (diode between 1-3) and the other against negative transients (diode between 2-3)?
 

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #6 on: April 21, 2023, 06:04:56 pm »
@Kim Got it, but why leaving out the second zener between pins 2 and 3 ? I was just thinking one of them protects against positive transients (diode between 1-3) and the other against negative transients (diode between 2-3)?

A single 6.8V zener will let the voltage swing between -0.7V and +6.8V...
ie: It'll clamp negative transients at -0.7V and positive transients at +6.8V

There is no reason the voltage would need to swing below ground in this design. The MCU's PB0 pin can't go below ground anyway. Hence I showed a single zener in my diagram. You could use the other one to protect another IO pin if needed.

 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #7 on: April 21, 2023, 06:08:29 pm »
The other thing is it's a dummy load on +12V.  Maybe that's intended, who knows.

Maybe it was meant to be a 10k, and it's a logic output going somewhere else but there's no net label or wire, and it was just... left and forgotten?  It surely didn't pass any kind of design review, in any case.

I wouldn't think there's much meaning to be extracted from it.  Was it supposed to connect to something?  Was it an in-progress schematic that was dropped in the middle?  Was it all a hallucination, was it made by human hands (or by their intent) at all?  Who knows; probably doesn't matter much.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #8 on: April 21, 2023, 06:40:17 pm »
@Kim Okay, but there area a number of FETs having two built-in zeners connected similarly to the diagram I have got. If only one is enough, why are they using two in series ?

Also, how would I go about preventing a D-G short in the first place ?

@Tim My load is a 12V lamp, so I guess he's just put 10 ohm in there for that reason...
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #9 on: April 21, 2023, 07:04:33 pm »
Oh it is a thing, alright.

...Wait, is *this* the design review?  Right now? 🤔

The usual way to avoid shorts is a suitable choice of MOSFET.  "Protected switch" types are popular in automotive application.  They offer modest peak current limiting, and transient and thermal limiting.

Tim
« Last Edit: April 21, 2023, 07:25:20 pm by T3sl4co1l »
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #10 on: April 21, 2023, 07:05:54 pm »
@Kim Okay, but there area a number of FETs having two built-in zeners connected similarly to the diagram I have got. If only one is enough, why are they using two in series ?

It allows for more flexibility. Those FETs can be used in many different products and in some cases being able to drive the gate negative is useful. But in your circuit that'll never happen. In fact, letting it swing -7.5V would be detrimental to protecting the MCU. Clamping it at -0.7V and limiting the current through the 4k7 resistor is much less stressful on the MCU's PB0 port than clamping it at -7.5V and letting much more current flow.
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #11 on: April 21, 2023, 08:24:40 pm »
Wait a minute. In a positive transient isn't the voltage regulator (will be of 5V variety) protected by  those didoes + resistor at entry  ? So that its ouptut will be at 5V and thus no more than 5V on FET's gate. So what good is the zener then ?
 

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #12 on: April 21, 2023, 09:33:56 pm »
In the modified circuit I posted, the zener is only useful for protecting the MCU if the FET failed with a Drain to Gate short.
Yes, the regulator is somewhat protected by that diode, resistor, & zener on it's input. If the regulator's output spiked enough to damage the FET via the MCU, the MCU would have been dead already.
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #13 on: April 21, 2023, 11:00:08 pm »
In that case I think the zener should be replaced with one that has a Vz lower than MCU pin absolute maximum = 5.5V. Not too low, so the FET gate won't get a lowered voltage in normal operation. Maybe a Vz = 4v7 or 5v1 will do fine.
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #14 on: April 21, 2023, 11:35:35 pm »
Just remove it -- it isn't doing anything in normal operation, and abnormal operation has other solutions.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #15 on: April 21, 2023, 11:43:14 pm »
Just be aware that zeners tend to start conducting a little bit before their rated voltage. So while a 4v7 zener might be rated at 4.7V @ 60mA, it might start drawing 1mA when the voltage across it reaches 4.4V causing a voltage drop across the resistor and thus less voltage for the FET gate.
Also, most MCUs have protection diodes on most of their IO pins that will shunt excess voltage to the supply rails. The key is not to have too much current flow, which is the job of the 4k7 resistor between the IO pin and the zener. What MCU are you using?
ie: If you had a 6V zener, and the FET had failed, that would mean there would be 0.3V (6 - 0.7 - 5V) across the 4k7 meaning only 64uA of current would flow into the IO pin which wouldn't harm it.

I agree with T3sl4co1l... The zener isn't really necessary unless you are super paranoid or gonna blow up a lot of FETs while experimenting.
« Last Edit: April 21, 2023, 11:45:06 pm by Kim Christensen »
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #16 on: April 22, 2023, 11:31:25 am »
This might be over my head, but I would like to learn how to protect that FET without a pre-packaged "protected switch". Maybe those 3 elements protecting the regulator can also be tweaked and made to protect the FET ?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #17 on: April 22, 2023, 04:34:16 pm »
You need a whole lot more circuitry to do that. At least a shunt resistor to sense current (and perhaps limit short-circuit current as well), perhaps an op-amp, and some logic to handle the on-off behavior (perhaps an edge triggered flip-flop, and a timer to hold it off in fault mode).  You can't measure the die temperature with ~zero delay, as the integrated kind can, so you must either calculate SOA in real time (measuring voltage and current, and multiplying them) or use worst-case figures (say, measuring current but assuming maximum voltage, or measuring voltage and limiting current to a reliable value).  And that'll be relative to an assumed maximum ambient temperature, or you measure and incorporate that into the calculation.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #18 on: April 22, 2023, 06:06:36 pm »
A low tech/effort way of protecting the FET would be to over spec the FET by a huge margin while also protecting it with a PTC fuse (current) and TVS (voltage).

Or you could just spend less money and use what T3sl4co1l suggested. For example, something like the NCV8403 might work for your application and it's going to be cheaper than DIYing or over spec-ing a part.
« Last Edit: April 22, 2023, 06:11:59 pm by Kim Christensen »
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #19 on: April 23, 2023, 05:20:25 pm »
How do these short circuits happen ? When the light bulb fails it wil fail open, no ?

Or it can be caused bymany other factors; maybe I should worry about it for not only the FET but the mcu and regulator also ?
 

Offline Kim Christensen

  • Super Contributor
  • ***
  • Posts: 1404
  • Country: ca
Re: ESD Zeners in this diagram ?
« Reply #20 on: April 23, 2023, 08:08:56 pm »
Quote
How do these short circuits happen ? When the light bulb fails it wil fail open, no ?
Depends on the application... For example, if the bulb was a turn signal in a car, it's most likely fail mode would be going open... But then there's the scenario where the car has a fender bender and the lamp is smashed and gets shorted out. Or the user splices in a trailer plug and overloads the circuit.
You can't design for every crazy scenario and at some point you're going to have to accept a certain amount of risk. So what is this circuit to be used for anyway?



 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #21 on: April 23, 2023, 09:55:51 pm »
It could also be exposed to transients.  Likely not the full gamut of say ISO-7637, but a subset perhaps. 

Shorted or crossed wiring faults can also happen, whether due to aging wiring, or rodent damage, or water damage, or etc.  Or the worst scourge of all: aftermarket parts and too-clever-for-their-own-good end users / shade-tree mechanics.

If we're talking tungsten light bulbs, the startup current might well look damn close to a short circuit.  Again, something an oversized MOSFET can handle, but given some massaging of the SOA, a current-limited circuit might be cheaper (smaller die area).  Assuming the control circuitry is low cost, of course (which it can be, if integrated and purchased in the millions qty -- as protected switches are).

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #22 on: April 23, 2023, 10:59:56 pm »
Heh, I suppose as an example of protection circuits, this might be interesting:
https://www.eevblog.com/forum/projects/transistors-die-pictures/msg4829513/#msg4829513

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #23 on: April 25, 2023, 01:17:53 am »
I am looking to add extra lights on my offroader... an old soviet era creature that would look terrible with leds, so I would probably want to stick to good old tungsten. Dim them by PWM depending on lighting conditions. Or not, it would make matters more complicated. Drive instead a variable number of headlights based on surrounding luminosity.

Since there already is a MCU, maybe I can hook the current sense resistor to it, interrupt, then... then what ?

How about the fastest fuse I can get (at reasonable prices) ?
« Last Edit: April 25, 2023, 02:43:28 pm by kellogs »
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #24 on: April 29, 2023, 04:57:48 pm »
"Protected switch" types are popular in automotive application.  They offer modest peak current limiting, and transient and thermal limiting.

Tim

Okay, point taken. So,

https://www.infineon.com/dgdl/Infineon-BTS7080-2EPA-DataSheet-v01_10-EN.pdf?fileId=5546d4625e763904015e941bf21e2dbe

They do not say it is good for negative transients but they do say it protects against reverse polarity. Until I get an answer from them (if ever):



Hello,

Looking into BTS7080-2EPA datasheet, i have got a question.

On page   7: "Power Supply Voltage VS -0.3 – 28 V "
On page 18: "Breakdown Voltage between GND and VS Pins in Reverse Battery -VS(REV) 16 – 30 V 1) IGND(REV) = 7 mA TJ = 150 °C"

I am not sure about "between GND and VS Pins" - since there is an R_GND on the diagram of 47 ohm recommended value, that would make the GND pin at roughly -0.33 V in a reversed battery situation. Do i understand well that the VS pin can actually withstand at least -16.33 V ?
If so, then will a properly designed diode clamp at less than |-16.33| V make the chip survive ISO type of negative transients  ?

Thank you



Attached the datasheet diagram for this device as well as what my diode clamp would look like.
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #25 on: April 30, 2023, 02:40:29 am »
Oh, high side switch?  Okay...

The odd thing about those is they're not ground referenced in the way you would think.  Only the logic input (and any fault or current sense outputs) need to be ground referenced, so they can just kinda hang that section down from VS.  Probably the bulk of the chip is referenced to the output (NMOS source)? Not sure exactly.  But anyway, that's what makes the voltage ratings seem weird.  With that in mind, consider the ratings and figure out an effective circuit for where ESD diodes are.  Or, consider the ratings effectively as zener diodes, at least for purposes of allowable voltages, not necessarily what happens when you exceed them.

And also because it's just logic floating around, referenced to wherever it is, the current draw for that stuff is small and just whatever; hence you can afford to add resistors to limit current, and much smaller TVS to clamp voltages at the device.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #26 on: April 30, 2023, 05:35:47 am »
Do you mean these Zeners ?

I have added my own... not sure what I am doing though.  :-//
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #27 on: April 30, 2023, 08:00:20 am »
Ah yeah, they have that diagram already, nice.

Huh. They show zener from internal gate to VS, which means it can never saturate. I think they mean an anti-series diode there, so they're only showing the maximum voltages, not the minimums.  At least with respect to that node.

Hm, matter of fact, they don't show nearly enough combinations of voltage ratings to describe that diagram. So I guess they mean that figure to describe that.

Oh, and Fig.11.

Oh they show the D-G diode on Fig.17, but not 31, weird.

Anyway what you added to the drawing, if R_DI is big enough to respect DO and DI current limits, and R_SENSE for IS limits, then a zener/TVS in that location (VS to GND) will limit device reversal safely.  Mind it needs a series diode so it doesn't short out the supply when positive..

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #28 on: April 30, 2023, 10:39:40 am »
I guess I can then rotate 180 degrees that diode and be done with it?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #29 on: April 30, 2023, 11:26:04 am »
Or use a clamp diode (doesn't need to be zener at that point).  That works if you can tolerate full reverse voltage across the relevant resistors, while respecting pin currents.  The advantage to a D+TVS is you can get more voltage range before those currents flow.

And, obviously the resistors need to be rated for whatever power/energy they absorb in the process; continuous reversal being worse than transient, and all that.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #30 on: May 01, 2023, 07:39:08 am »
How does this situation change if I put in a SM8S15A load-ump grade TVS diode across Vs - chasis GND (not GND pin of the protected switch chip ) ? I figure it will also clamp negative transients to its Vf, meaning less than one Vf from Vs to GND pin of the protected switch, hence no further protection needed at the protected switch IC. Or ?

And in case I figured the previous thing correctly, should I also swap R_gnd for a lower value so as to ensure the 7 mA flowing into the GND pin during negative spikes ?
« Last Edit: May 01, 2023, 07:47:22 am by kellogs »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #31 on: May 01, 2023, 08:58:41 am »
Right.

But then you fail reverse jump start -- if it's a part of your requirements, that is.  Perhaps a series diode or MOSFET is adequate to put that back in.

R_gnd only needs to be low enough to keep GND "GND-y" over normal operating currents, and high enough to limit maximum current in all conditions (which will be small or negligible with such a diode clamping max and min like that).  Perhaps it can be removed entirely in this case.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #32 on: May 01, 2023, 09:14:56 pm »
I was thinking about floating gate in case of cold cranking - fixable by weak pull down resistor at IN digital pins, right? Then I have come into page 38 at the bottom:

Quote
Note:
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground
path is available, which could keep the device operational during loss of device ground.


Err... not  a big issue, is it ?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #33 on: May 02, 2023, 04:53:45 am »
I assume you'll be using common (hard wired i.e. PCB) ground with the source (MCU?), so that's N/A.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #34 on: May 02, 2023, 08:40:37 am »
I was thinking more of a rodent and the GND wire, or loose connection to chassis. 
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #35 on: May 02, 2023, 01:41:18 pm »
If there's simply not enough power coming into the box, nothing is running..?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #36 on: May 02, 2023, 04:27:53 pm »
Right.

But then you fail reverse jump start -- if it's a part of your requirements, that is.  Perhaps a series diode or MOSFET is adequate to put that back in.

Tim

Like so ? The Diodes combo should protect against everything ISO except cold cranking I think.
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #37 on: May 02, 2023, 06:01:35 pm »
Is additional reverse protection really necessary when D1 already clamps reverse to a few volts tops?  That PMOS isn't doing much...

Reverse jumpstart isn't part of ISO 7637-2, but shows up in other (possibly customer specific) standards.  You might if nothing else want a fuse there, in case of accidental wrong wiring say (or you already intend a fuse and just don't show it here, that's fine).

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #38 on: May 02, 2023, 08:21:04 pm »
A fuse... so as to protect the big TVS ? ...nah

How about now ?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #39 on: May 02, 2023, 08:57:12 pm »
Hm, PMOS is backwards too. And you probably want a gate resistor, and G-S zener to limit Vgs, anyway.  Why two PMOS?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #40 on: May 02, 2023, 09:04:27 pm »
The two PMOS are there to protect against reverse polarity.
Gate resisotr, ok. How big ?
Vgs limited for both FETs by D2, through body diodes (?)
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #41 on: May 02, 2023, 09:14:17 pm »
If you follow the body diodes you'll find they aren't doing what you thought they were doing...

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #42 on: May 02, 2023, 09:22:21 pm »
Not understand. Is it not

V_gs = V_clamp_D2 + V_f_D3 + V_f_body

for negative spikes, on each of the FETs ?
« Last Edit: May 02, 2023, 09:32:54 pm by kellogs »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #43 on: May 03, 2023, 05:18:10 am »
Source is the one with the triangle/arrow, so, the input is allowed to be very negative relative to gate.  Body diode will pull down on D2+D3 as a secondary effect, but mind their inductance, which still allows high transient Vgs.

PMOS is pointing the wrong way because you want the body diode pointing inwards, then the channel enhances in parallel making it a synchronous rectifier for positive Vin.  This can be placed before the load dump TVS if you like, because the body diode handles surge easily (for an adequately sized part; check ratings).  Then the second TVS and second PMOS are obviated, win win.

Vgs protection you just want referenced to G and S and nothing else. 10k-100k is a typical value, it's non-critical.



Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: kellogs

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #44 on: May 03, 2023, 01:01:24 pm »

Oh, man! A single MOSFET can do the job, neat! I still want to keep the load-dump grade diode though, multiple parts to be protected by it

This can be placed before the load dump TVS if you like, because the body diode handles surge easily (for an adequately sized part; check ratings). 

Tim

Like so ? Body diode should be not conducting, no ? The DS channel is already open when a spike occurs (unless terribly unlucky).

1774295-0" alt="" class="bbc_img" />

I think the FET will be able to ride through a 0.75 ohm 101V peak 400 ms load dump event.

V_clamp = 24.4V leaving some 75V over 0.75 ohm = 100 A through the FET and TVS diode. Looking at teh SOA graph the FET should survive it. V_gss is pretty close at 25V though.

1774301-1" alt="" class="bbc_img" />

Also it should survive every other spike there is, positive or negative. Plus battery reversal. Is this good enough ?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #45 on: May 03, 2023, 02:36:37 pm »
Yeah, that should be fine.

I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.

Only 30V though; so a -200V pulse comes along while it's otherwise humming along at 14.4V, what happens?

Tim
« Last Edit: May 03, 2023, 02:38:11 pm by T3sl4co1l »
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #46 on: May 03, 2023, 02:55:34 pm »
Only 30V though; so a -200V pulse comes along while it's otherwise humming along at 14.4V, what happens?

Tim

I guess V_source_pin will rise because inductance and eventually be clamped by diode at 24.4V
Then V_drain_pin keeps going down until V_ds = -224.4V ?


I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.


Zener + R, in parallel with the fat TVS ?
Reattached. First diodes group (zener + antiseries rectifier) are going to clamp negatvie spikes to some 2 + 1.5 = 3.5V, so that V_ds will stay at -(3.5 + 24.4) = -28.4V

Thanks a lot for your input!
« Last Edit: May 03, 2023, 04:12:06 pm by kellogs »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #47 on: May 03, 2023, 04:32:50 pm »
Why would source rise? The input is pulling it down, dI/dt is negative..?

Note that channel remains conductive until Vgs < Vgs(th), which especially with the gate resistor, doesn't happen quickly.  So either input capacitance (not shown) or the big TVS absorbs fast transients.  Over longer time scales (100s us?), Vgs decays, Vout doesn't drop much below zero, and Vin is allowed to go negative as far as it wants (until clamped by input TVS or PMOS breakdown).

An input antiparallel diode would seem to suffice, if you don't need to worry about reverse polarity (but then, why the PMOS at all?); and if you do, then a 30V (or less) peak clamping TVS (with series diode as shown) will protect the PMOS.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #48 on: May 03, 2023, 05:02:35 pm »
Well, i thought it would rise because

Quote
Body diode will pull down on D2+D3 as a secondary effect, but mind their inductance,

and that inductance would oppose the negative dI/dt... Anyway, is my last schematic fine then ? I can perhaps pick first Zener TVS (instead of zener) a bit higher than 2V so that |Vz+Vf| < 30V and off i go
« Last Edit: May 03, 2023, 05:29:13 pm by kellogs »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #49 on: May 03, 2023, 06:53:53 pm »
The inductance comment regards faster pulses, like ESD.  Where the inductance of these components will be important.  Inductance is less or unimportant for slower pulses.

You'll have a hard time finding a 2V zener. Which also blows the fuse if you apply -12V. But a 15V zener there would seem to be fine, wouldn't it?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #50 on: May 03, 2023, 07:53:39 pm »
No, no more Zener. I am placing a smaller TVS there on the branch with the V_rrm = 300V rectifier.

Maybe a SM6T15AY; It has
V_clamp_max = 27.2V or 21.2V depending on waveform: 8/20 or 10/1000
V_br_min = 14.3V

ISO transient -150V @ 10 ohm @ 10/2000 -> roughly some 13.5A max through that branch; for my rectifier -> some 2.7V = V_f, with V_clamp closer to 21.2V than to 27.2V -> happy FET
ISO transient -220V @ 50 ohm @ ... 0.005/0.015 or 0.005/100 (?). ISO not clear on it -> roughly some 4A max through that branch; for my rectifier -> some 2V = V_f, with V_clamp closer to... probably 27.2V -> a bit stressed FET

I think both the FET and any fuse stay roughly happy :)
 

Offline kellogsTopic starter

  • Regular Contributor
  • *
  • Posts: 73
  • Country: ro
Re: ESD Zeners in this diagram ?
« Reply #51 on: July 30, 2023, 11:58:49 am »
Yeah, that should be fine.

I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.



Ugh, excuse me, but...

Just had a look over the normalized ZthC for 400 ms and and single pulse - it is around 0.6

RthC = 1.4 C/W and average I ~= 55A (load dump). For Rds ~= 5 mohm:

T_j = 0.6 * 1.4 * 3025 * 0.005 + T_c = 12.7 degrees over case temperature.

But then there is the case-ambient thermal resistance as well, and much bigger. Should I worry about it ?
« Last Edit: July 30, 2023, 01:18:29 pm by kellogs »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21854
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: ESD Zeners in this diagram ?
« Reply #52 on: July 30, 2023, 07:21:34 pm »
Oh, you probably want a D2PAK then, not one of those PDFN5X6 variants.  I don't know why ZthJC continues going up past 10ms, *possibly* the source bond clip soaking some heat, but in general ZthJC (to *case*) is over and done in a couple ms (here, about 10, less the source clip), and then it's up to whatever's around it.

Which, if you don't have solid metal backing up the tab, that's the end of it, ZthJA skyrockets into the 100ms range.  You need ZthJA to do this estimation, not JC.  (Note, it's no worse than 1:1, or 10x Zth for 10x t, being the constant heat capacity line assuming no new material is being heated.)

Anyway, D2PAK is more material.  Thicker tab.  That's it.  Chip can be identical, same SOA.  Could also use a metal core PCB, or one of those boutique fabs with metal pillars buried into it (or machined or whatever), but... right.

Also, you probably want to do a real simulation, because pulse power varies with time, and so does heat as it's spreading out.  A transient thermal model can be fitted to the curve, and then connected to some manner of heatsink (to the extent one can be turned into a transient model).  You will most likely find PCB alone isn't enough, and a direct clamped heatsink of some substance is required (even just a slug of metal).

Or put the TVS out in front, in series with a rectifier big enough to handle the surge automatically (same idea, it'll just have a higher Tj(max) and thicker leadframe).  Saves MOSFET size.  The rect + FET is going to be bigger than just using a larger MOSFET though.

Note that TO-220 (standing without a heatsink) is about the same as D2PAK, if verticality is any help.  And can be clamped to a slug of metal, or heatsink proper, if needed.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf