Author Topic: ESD Zeners in this diagram ?  (Read 3710 times)

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Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #25 on: April 30, 2023, 02:40:29 am »
Oh, high side switch?  Okay...

The odd thing about those is they're not ground referenced in the way you would think.  Only the logic input (and any fault or current sense outputs) need to be ground referenced, so they can just kinda hang that section down from VS.  Probably the bulk of the chip is referenced to the output (NMOS source)? Not sure exactly.  But anyway, that's what makes the voltage ratings seem weird.  With that in mind, consider the ratings and figure out an effective circuit for where ESD diodes are.  Or, consider the ratings effectively as zener diodes, at least for purposes of allowable voltages, not necessarily what happens when you exceed them.

And also because it's just logic floating around, referenced to wherever it is, the current draw for that stuff is small and just whatever; hence you can afford to add resistors to limit current, and much smaller TVS to clamp voltages at the device.

Tim
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #26 on: April 30, 2023, 05:35:47 am »
Do you mean these Zeners ?

I have added my own... not sure what I am doing though.  :-//
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #27 on: April 30, 2023, 08:00:20 am »
Ah yeah, they have that diagram already, nice.

Huh. They show zener from internal gate to VS, which means it can never saturate. I think they mean an anti-series diode there, so they're only showing the maximum voltages, not the minimums.  At least with respect to that node.

Hm, matter of fact, they don't show nearly enough combinations of voltage ratings to describe that diagram. So I guess they mean that figure to describe that.

Oh, and Fig.11.

Oh they show the D-G diode on Fig.17, but not 31, weird.

Anyway what you added to the drawing, if R_DI is big enough to respect DO and DI current limits, and R_SENSE for IS limits, then a zener/TVS in that location (VS to GND) will limit device reversal safely.  Mind it needs a series diode so it doesn't short out the supply when positive..

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #28 on: April 30, 2023, 10:39:40 am »
I guess I can then rotate 180 degrees that diode and be done with it?
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #29 on: April 30, 2023, 11:26:04 am »
Or use a clamp diode (doesn't need to be zener at that point).  That works if you can tolerate full reverse voltage across the relevant resistors, while respecting pin currents.  The advantage to a D+TVS is you can get more voltage range before those currents flow.

And, obviously the resistors need to be rated for whatever power/energy they absorb in the process; continuous reversal being worse than transient, and all that.

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #30 on: May 01, 2023, 07:39:08 am »
How does this situation change if I put in a SM8S15A load-ump grade TVS diode across Vs - chasis GND (not GND pin of the protected switch chip ) ? I figure it will also clamp negative transients to its Vf, meaning less than one Vf from Vs to GND pin of the protected switch, hence no further protection needed at the protected switch IC. Or ?

And in case I figured the previous thing correctly, should I also swap R_gnd for a lower value so as to ensure the 7 mA flowing into the GND pin during negative spikes ?
« Last Edit: May 01, 2023, 07:47:22 am by kellogs »
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #31 on: May 01, 2023, 08:58:41 am »
Right.

But then you fail reverse jump start -- if it's a part of your requirements, that is.  Perhaps a series diode or MOSFET is adequate to put that back in.

R_gnd only needs to be low enough to keep GND "GND-y" over normal operating currents, and high enough to limit maximum current in all conditions (which will be small or negligible with such a diode clamping max and min like that).  Perhaps it can be removed entirely in this case.

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #32 on: May 01, 2023, 09:14:56 pm »
I was thinking about floating gate in case of cold cranking - fixable by weak pull down resistor at IN digital pins, right? Then I have come into page 38 at the bottom:

Quote
Note:
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground
path is available, which could keep the device operational during loss of device ground.


Err... not  a big issue, is it ?
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #33 on: May 02, 2023, 04:53:45 am »
I assume you'll be using common (hard wired i.e. PCB) ground with the source (MCU?), so that's N/A.

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #34 on: May 02, 2023, 08:40:37 am »
I was thinking more of a rodent and the GND wire, or loose connection to chassis. 
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #35 on: May 02, 2023, 01:41:18 pm »
If there's simply not enough power coming into the box, nothing is running..?

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #36 on: May 02, 2023, 04:27:53 pm »
Right.

But then you fail reverse jump start -- if it's a part of your requirements, that is.  Perhaps a series diode or MOSFET is adequate to put that back in.

Tim

Like so ? The Diodes combo should protect against everything ISO except cold cranking I think.
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #37 on: May 02, 2023, 06:01:35 pm »
Is additional reverse protection really necessary when D1 already clamps reverse to a few volts tops?  That PMOS isn't doing much...

Reverse jumpstart isn't part of ISO 7637-2, but shows up in other (possibly customer specific) standards.  You might if nothing else want a fuse there, in case of accidental wrong wiring say (or you already intend a fuse and just don't show it here, that's fine).

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #38 on: May 02, 2023, 08:21:04 pm »
A fuse... so as to protect the big TVS ? ...nah

How about now ?
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #39 on: May 02, 2023, 08:57:12 pm »
Hm, PMOS is backwards too. And you probably want a gate resistor, and G-S zener to limit Vgs, anyway.  Why two PMOS?

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #40 on: May 02, 2023, 09:04:27 pm »
The two PMOS are there to protect against reverse polarity.
Gate resisotr, ok. How big ?
Vgs limited for both FETs by D2, through body diodes (?)
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #41 on: May 02, 2023, 09:14:17 pm »
If you follow the body diodes you'll find they aren't doing what you thought they were doing...

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #42 on: May 02, 2023, 09:22:21 pm »
Not understand. Is it not

V_gs = V_clamp_D2 + V_f_D3 + V_f_body

for negative spikes, on each of the FETs ?
« Last Edit: May 02, 2023, 09:32:54 pm by kellogs »
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #43 on: May 03, 2023, 05:18:10 am »
Source is the one with the triangle/arrow, so, the input is allowed to be very negative relative to gate.  Body diode will pull down on D2+D3 as a secondary effect, but mind their inductance, which still allows high transient Vgs.

PMOS is pointing the wrong way because you want the body diode pointing inwards, then the channel enhances in parallel making it a synchronous rectifier for positive Vin.  This can be placed before the load dump TVS if you like, because the body diode handles surge easily (for an adequately sized part; check ratings).  Then the second TVS and second PMOS are obviated, win win.

Vgs protection you just want referenced to G and S and nothing else. 10k-100k is a typical value, it's non-critical.



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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #44 on: May 03, 2023, 01:01:24 pm »

Oh, man! A single MOSFET can do the job, neat! I still want to keep the load-dump grade diode though, multiple parts to be protected by it

This can be placed before the load dump TVS if you like, because the body diode handles surge easily (for an adequately sized part; check ratings). 

Tim

Like so ? Body diode should be not conducting, no ? The DS channel is already open when a spike occurs (unless terribly unlucky).

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I think the FET will be able to ride through a 0.75 ohm 101V peak 400 ms load dump event.

V_clamp = 24.4V leaving some 75V over 0.75 ohm = 100 A through the FET and TVS diode. Looking at teh SOA graph the FET should survive it. V_gss is pretty close at 25V though.

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Also it should survive every other spike there is, positive or negative. Plus battery reversal. Is this good enough ?
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #45 on: May 03, 2023, 02:36:37 pm »
Yeah, that should be fine.

I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.

Only 30V though; so a -200V pulse comes along while it's otherwise humming along at 14.4V, what happens?

Tim
« Last Edit: May 03, 2023, 02:38:11 pm by T3sl4co1l »
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #46 on: May 03, 2023, 02:55:34 pm »
Only 30V though; so a -200V pulse comes along while it's otherwise humming along at 14.4V, what happens?

Tim

I guess V_source_pin will rise because inductance and eventually be clamped by diode at 24.4V
Then V_drain_pin keeps going down until V_ds = -224.4V ?


I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.


Zener + R, in parallel with the fat TVS ?
Reattached. First diodes group (zener + antiseries rectifier) are going to clamp negatvie spikes to some 2 + 1.5 = 3.5V, so that V_ds will stay at -(3.5 + 24.4) = -28.4V

Thanks a lot for your input!
« Last Edit: May 03, 2023, 04:12:06 pm by kellogs »
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #47 on: May 03, 2023, 04:32:50 pm »
Why would source rise? The input is pulling it down, dI/dt is negative..?

Note that channel remains conductive until Vgs < Vgs(th), which especially with the gate resistor, doesn't happen quickly.  So either input capacitance (not shown) or the big TVS absorbs fast transients.  Over longer time scales (100s us?), Vgs decays, Vout doesn't drop much below zero, and Vin is allowed to go negative as far as it wants (until clamped by input TVS or PMOS breakdown).

An input antiparallel diode would seem to suffice, if you don't need to worry about reverse polarity (but then, why the PMOS at all?); and if you do, then a 30V (or less) peak clamping TVS (with series diode as shown) will protect the PMOS.

Tim
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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #48 on: May 03, 2023, 05:02:35 pm »
Well, i thought it would rise because

Quote
Body diode will pull down on D2+D3 as a secondary effect, but mind their inductance,

and that inductance would oppose the negative dI/dt... Anyway, is my last schematic fine then ? I can perhaps pick first Zener TVS (instead of zener) a bit higher than 2V so that |Vz+Vf| < 30V and off i go
« Last Edit: May 03, 2023, 05:29:13 pm by kellogs »
 

Offline T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #49 on: May 03, 2023, 06:53:53 pm »
The inductance comment regards faster pulses, like ESD.  Where the inductance of these components will be important.  Inductance is less or unimportant for slower pulses.

You'll have a hard time finding a 2V zener. Which also blows the fuse if you apply -12V. But a 15V zener there would seem to be fine, wouldn't it?

Tim
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