Battery power

[hedley]

Tried to have simple wired or battery backup for SRAM . The ram requires CS/ to be high for low power standby . Problem is CS/ is an output from the processor which is unpowered . Strangely this causes 1ma of current sink ??. If I lift the pin on the processor I have low power .

Any input from the smart posters will bE much appreciated

Regards
Hedley@cynaps.co.za

[NiHaoMike]

Add a small MOSFET (2N7000 is ideal) in series with the drain going to the RAM, source going to the processor, and gate going to the processor (active low) reset.

[hedley]

Perhaps some clarification

1. The battery ( Vbat ) powers a pullup resistor 10K  on the CS/ line and the VCC of the Ram chip. This means the only powered devices on the board are the Static ram VCC the wired OR diode , and the pullup for CS/.

If I connect the Mosfet as suggested , the gate will be at or close to 0V as the processor and the reset circuit have no power ( perhaps I misunderstood the answer / suggestion ) .

I just can not figure out how the CS/ output pin  of the NON powered processor can sink 1mA . I thought it may be leakage current but if so it seems very high. I cant simulate this condition on Pspice and further the datasheets don't really set out how the device behaves under no power. I am just trying to solve a problem with an OLD legacy product where the processor is an Intel 80c188ec ( long discontinued ) and the ram chip is an K6T4008 CIC . It is a bit embarrassing to get stuck on ohms law circuit analysis problems but sometimes that is the nature of the game.

[hedley]

here is the basic circuit . Note the Processor is not powered yet sinks +- 1000uA.

[glarsson]

I just can not figure out how the CS/ output pin  of the NON powered processor can sink 1mA .

Protection / parasitic diodes between the output pin and processor Vcc?

[David Hess]

I just can not figure out how the CS/ output pin  of the NON powered processor can sink 1mA .

Protection / parasitic diodes between the output pin and processor Vcc?

The 10k resistor would limit current to about 250 microamps worst case.

What might be happening is that the 10k resistor pulls -CS up high enough for the SRAM itself to draw excess power possibly through just the -CS pin's input buffer.  When operating on 2.5 volts from 3.0 volts through the diode, the input threshold voltage will only be 1.25 volts or lower if the SRAM has TTL compatible inputs.  The processor's output protection diodes would allow its output to be pulled up about 0.6 volts from ground.  No part numbers were given so this is difficult to evaluate.

NiHaoMike has the right idea.  A gate or transistor must be used between the processor and SRAM -CS pin to prevent excessive current through the pull-up resistor which would defeat the purpose of using a micropower SRAM in standby.  I prefer the gate method which is much faster and lower power without a pull-up resistor.

[hedley]

‘Thanks for responses . I would agree that 3v with 10k should mean 300uA max . When circuit connected as per diagram , multimeter ( fluke 87v ) in séries with vbat shows 1045uA . I then lift the processor CS pin off the board and the current goes down to ~40-50 uA.

I have ordered the fet and will try out . For standby you need power to the ram chip > 2V and CS/ must be no more than .2 V less than that ie 1.8 . I my case I have vbat of 3v and CS/ at the same so all works as advertised until that processor pin connected .

[hedley]

Page 3 seems to point me in the right direction.

http://www.cypress.com/file/38171/download

[David Hess]

Page 3 seems to point me in the right direction.

http://www.cypress.com/file/38171/download

That shows the problem.  A pull-up resistor should be used with the collector/drain of a discrete transistor or an open collector/drain logic output which lacks the high side protection diode as with logic which is high voltage tolerant on its outputs.

I prefer to use a 74HC00 or faster CMOS logic if necessary to actively drive the -CS pin even when on backup power.  The CMOS logic is powered by the same backed up supply as the memory but being CMOS logic, its quiescent current is very low so battery drain is not significantly increased.  If using NAND gates, one gate inverts the original -CS signal and the second gate combines the inverted -CS and active low power fail signal which of course fails low when no power is present.  This Maxim example shows the idea.