Decoupling capacitors and perceived wisdom

[SiliconWizard]

Paralleling several small SMD caps in similar packages rarely makes any sense as they have a very similar parasitic inductance and ultra-low ESR. At worst, that can cause more issues than good due to multiple resonant frequencies (as shown in the video), but in many cases, it has few downsides but practically no benefit.

After that, there are many specific cases (that's called engineering), but seeing, say, a modest MCU with VDD pins bypassed with a 1 µF ceramic and 100 nF ceramic in the same package or barely larger for the 1 µF (say 0603 for the 1 µF and 0402 for the 100 nF), that makes almost no sense. Might help if you're very tight on routing though, to allow the smaller cap as close to the pin as possible. So, yeah, sometimes it may not seem to make any electrical sense just based on the schematic, but considering the PCB layout, it may.

Bottom line is, if you half know why you do things, you're better off than just using cargo cult approaches. Shocker.

[Siwastaja]

Where is your evidence?

Nowhere, of course. Let me rephrase: This capacitor thing is largely cargo cult.

We could prove individual design examples as either better or worse case-by case. Say, build two prototypes, test analog performance, go to EMC lab. A lot of work, and maybe 10-20k€ for each case. Then we could collect statistics for the general trend. Even more work. Neither of us is willing to provide such proof.

I totally agree with you that some specific circuit examples probably do work better with exact parts list as given, than simply replacing everything with 0402 1µF. The following traits increase the probability that this is the case:
* Special IC with critical high-frequency performance
* Exact capacitor part numbers given, not just values
* Capacitor values are not in multiples of ten, but more "weird" values, such as 68nF and 1uF, and not 10n || 100n || 1u

It is possible some reference design went "for the dip" as I call it. Maybe, say, PLL on FPGA is sensitive to excess impedance at some exact frequency.

Then again, for something like an FPGA, I also suspect that choosing different oscillator frequency, or different PLL configurations, affect the exact frequency where most bypassing is needed. In such cases the capacitors should be adjusted, too. If going "for the dip", that is. And as I said, careful tuning is required and component tolerances are risky. I claim this is best done on a prototype looking at say eye diagram, spectrum analyzer screen, or at EMC lab, soldering alternative components until exact best spot performance is found, and keeping track of exact part number used, making sure to use parts with best possible tolerances and stability - basically meaning C0G if at all possible. Consider the effect of MLCC aging on capacitance value, and thus SRF, on X7R! For a robust design, you would try to take this aging into account, and aim for the correct side of the dip, so that it does not soon drift out of the required value range.

I redefine my claim that if we pick 100 random designs from perfectly randomized appnotes, datasheets and other professional literature which show usage of three different ceramic capacitance values in parallel, 95 are cargo cult: where this strategy has no benefit whatsoever, and possibly in significant (10-20?) of them, is seriously detrimental to analog/radio performance or EMC.

We need to distinguish between generic wide-bandwidth bypassing, and utilizing SRF dips for narrow-band bypassing. Two different things. The common "wisdom" that by combining enough capacitor values you "cover the entire band" is seriously misled, and caused simply by looking at impedance graphs in isolation without realizing they have different Y axis. See reply #20 for an example of the typical misconception.

[Nominal Animal]

The obvious errors found in datasheets indicates "very likely have done" is quite optimistic.  It may be so in some specific manufacturers' specific product lines, but I'm much less convinced it is true in general.  For many cheaper microcontrollers, decoupling capacitor recommendations seem to be based on some random engineer saying "I tried 100nF and it seems to work, so let's recommend that in the datasheet".

And how do you get to the conclusion it is random?

I did not write the capacitor value or recommendation is random, I wrote that for many cheaper microcontrollers, the recommendations seem to be written by a random engineer spending minimal effort on it.  But the question "conclusion based on what" is a valid, good one.

First, let's start with a counterexample: Microchip PIC16F152 series.  Not only does it have specific recommendations in the datasheet, it also explains why, and when to add further decoupling and bulk capacitance.  It is the detail, options, and reasoning behind the recommendations that makes it seem reliable and very useful even to a hobbyist like myself.

Next, an actual example of suspicious recommendation: Silicon Labs EFM80BB50 series, which says precisely "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible."  That's it.  Considering the core runs at about 50 MHz at 5V drawing about 3.3mA, that recommendation just does not make sense.  Rather, it sounds like that is what they always use when testing the design, and haven't characterized the power delivery network any further.  Put simply, to me it sounds like "do it this way because we haven't even considered anything else nor measured anything".

If I were to use the EFM80BB50, I'd look elsewhere for guidance on the supply bypassing.  The imperative statement is too obtuse to be taken as serious design advice or good engineering practice.

[ejeffrey]

Paralleling several small SMD caps in similar packages rarely makes any sense as they have a very similar parasitic inductance and ultra-low ESR. At worst, that can cause more issues than good due to multiple resonant frequencies (as shown in the video), but in many cases, it has few downsides but practically no benefit.

After that, there are many specific cases (that's called engineering), but seeing, say, a modest MCU with VDD pins bypassed with a 1 µF ceramic and 100 nF ceramic in the same package or barely larger for the 1 µF (say 0603 for the 1 µF and 0402 for the 100 nF), that makes almost no sense. Might help if you're very tight on routing though, to allow the smaller cap as close to the pin as possible. So, yeah, sometimes it may not seem to make any electrical sense just based on the schematic, but considering the PCB layout, it may.

Multiple capacitors in parallel can help because parallel inductors reduce the impedance.  What doesn't (usually) make sense is to use different capacitance values, but a totally reasonable process is:

1) pick the smallest package you are comfortable with (say 0402)
2) Pick the highest value capacitor you can get in that package cheaply
3) Use as many instances in parallel as you need to get the desired impedance
4) If needed have a bank of bulk capacitors somewhere on the PCB with enough capacitance and low enough ESR for the entire PCB. 

Resonances can be a problem so _if_ you parallel capacitors it's something you should at least think about.

Now, IC packages pins have inductance too.  In many cases it's comparable to the inductance of a capacitor.  That's why high power digital devices have lots of power and ground pins.  So it's a good bet that you *rarely* need more decoupling capacitors than power pins.

Bottom line is, if you half know why you do things, you're better off than just using cargo cult approaches. Shocker.

I'm not sure about that.  It's good to understand the underlying mechanism, but it's actually extremely difficult to solve what you *really* need.  It's hard to design, hard to simulate, and hard to measure.  Sometimes there is no way around it, but following simple rules of thumb like "add one 100 nF capacitor per power pin" is usually overkill, and sometimes insufficient, but a lot of times you can just do that and not worry about it.   It's rarely the best thing you can do, but it's often good enough.

[Nominal Animal]

This PDF log of experiments with decoupling capacitors by Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely.  See e.g. page 6, using 22µF 0805 and 100nF 0402 with plenty of vias to ground plane, on a 50Ω stripline, so there is some inductance also in the decoupling loop.  The one on page 18 with a 20-pin DIP socket with some (tantal?) cap diagonally shows how adding a 0805 100nF creates a clear antiresonance peak where you'd expect the dip to be.

[thm_w]

This whole capacitor thing is typical example of cargo cult.

Where is your evidence? And don't point to the video linked to in the first post. It is a school book example of simplifying a model to the point where it is completely wrong.

You said yourself on die capacitors deal with anything >10MHz, Bogatin says the same. So why would 1nF or 10nF make any difference? Maybe FPGA is a special case that has poor on die decoupling?
The vast majority of designs use basic parts, and have these cult recommendations, so its fairly clear they were not extensively analyzed. Exceptions can exist.

https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values

[Siwastaja]

Multiple capacitors in parallel can help because parallel inductors reduce the impedance.  What doesn't (usually) make sense is to use different capacitance values, but a totally reasonable process is:

Yes! If you put 100n || 10n || 1n in parallel, you will see slight improvement in HF for each added capacitor, sure. But this is indeed because of the paralleled inductances (assuming, you can find good spot in the layout for each capacitor): you get the same overall HF performance with 100n || 100n || 100n, plus as an added benefit, better bypassing at lower frequencies.

So sprinkling a lot of capacitors all over the place is generally a good idea: just like sprinkling vias, but you don't normally want different values on the same bus to do that.

Practically though, it might be that only one of the capacitors is at the optimum placement. If the added ones have extra inductance from layout, then they provide diminishing returns. And herein lies the danger of the cargo cult solution: say you use 100n || 10n || 1n in parallel. You easily think that the 1n is the one that must be placed at the "best spot" because it bypasses "highest frequencies". Wrong! 100n bypasses high frequency just as well. Put that closest. If you then need to use 10n or 1n to "satisfy recommendations" (could be as well cardboard capacitors), place them further away. Cardboard would be better, avoiding risk of resonances, but I don't know how often that risk realizes.

And if you really have that case that you need 1µ for wide-band bypassing and a 330pF C0G for handling a specific problem frequency, then... they both need to be at optimum locations.

[Siwastaja]

This PDF log of experiments with decoupling capacitors by Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely.  See e.g. page 6,

Wow! That's a pretty serious price to pay for the "superior" "recommended" "solution".

[tggzzz]

This PDF log of experiments with decoupling capacitors by Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely.  See e.g. page 6, using 22µF 0805 and 100nF 0402 with plenty of vias to ground plane, on a 50Ω stripline, so there is some inductance also in the decoupling loop.  The one on page 18 with a 20-pin DIP socket with some (tantal?) cap diagonally shows how adding a 0805 100nF creates a clear antiresonance peak where you'd expect the dip to be.

That cap-in-a-socket was, from memory of 45 years ago, a simple ceramic.

Back then it was often LSTTL on a 2 layer board, and the one-cap-per IC was novel and controversial and often omitted, and that could result in marginal operation. In such cases those sockets could be retrofitted without respinning the PCB, a major advantage when using red-blue rubylith tape for the layout.

I'd be interested in seeing the effectiveness of a similar concept, the Rogers Micro-Q capacitors. They too fitted under ICs but didn't need a socket and had a construction much more like a transmission line or groundplane. Difficult to find pictures now, but see US patent 4734819

[Siwastaja]

This is the generic (simplified) concept: three impedance curves, each have same total C, each have same package size

Red: single large capacitor
Green: Multiple same capacitors with same total capacitance as red
Blue: Multiple different value capacitors with same total capacitance

[nctnico]

This PDF log of experiments with decoupling capacitors by Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely.  See e.g. page 6, using 22µF 0805 and 100nF 0402 with plenty of vias to ground plane, on a 50Ω stripline, so there is some inductance also in the decoupling loop.  The one on page 18 with a 20-pin DIP socket with some (tantal?) cap diagonally shows how adding a 0805 100nF creates a clear antiresonance peak where you'd expect the dip to be.

The problem with this experiment is that it is not a representative model of how capacitors are mounted on the board in a real circuit. So the results are not representative. You need to (at least) include trace inductance, via inductance, model the source (regulator) and load (chip(s) ) as well in order to get valid results. The impedances are so low that the circuit board itself forms a component as well. So you can't leave the circuit board out. The creator of the video linked to in the first post fell into the same trap. As I wrote before: A PDN network looks more like a bunch of cascaded elliptic, low-pass LC filters. These filters are quite sensitive to component values and need proper input and output impedance matching.

[Nominal Animal]

The problem with this experiment is that it is not a representative model of how capacitors are mounted on the board in a real circuit. So the results are not representative.

But somehow one should blindly trust a data sheet where the statement "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible" is all that is said about PDN/decoupling capacitors?

Yeah, no.  I think your opinion on this is nonsensical and defenseless.

[nctnico]

This whole capacitor thing is typical example of cargo cult.

Where is your evidence? And don't point to the video linked to in the first post. It is a school book example of simplifying a model to the point where it is completely wrong.

You said yourself on die capacitors deal with anything >10MHz, Bogatin says the same. So why would 1nF or 10nF make any difference? Maybe FPGA is a special case that has poor on die decoupling?
The vast majority of designs use basic parts, and have these cult recommendations, so its fairly clear they were not extensively analyzed. Exceptions can exist.

https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values

Quote from the article:
Do not be lulled into thinking that three different values of capacitors is a robust strategy, or that three capacitors all the same value is more robust. Without a system level analysis, they both may be equally acceptable, equally marginal, or fail from the same faults.

[Siwastaja]

The problem with this experiment is that it is not a representative model of how capacitors are mounted on the board in a real circuit.

Of course, but example schematics that just show paralleled different values are useless, because as this experiment demonstrates, the layout is important, and when using different capacitor values in parallel then it's even more important because with different values of C, parasitic L easily drives it into resonance as shown (page 6 vs 7). You have probably worked with some very good and well thought out recommendations which include part numbers and layout guidance. But that is the rare exception, unfortunately.

[tszaboo]

This PDF log of experiments with decoupling capacitors by Gerhard Hoffmann in 2007 shows the parallel different-valued capacitor antiresonance issues nicely.  See e.g. page 6, using 22µF 0805 and 100nF 0402 with plenty of vias to ground plane, on a 50Ω stripline, so there is some inductance also in the decoupling loop.  The one on page 18 with a 20-pin DIP socket with some (tantal?) cap diagonally shows how adding a 0805 100nF creates a clear antiresonance peak where you'd expect the dip to be.

The problem with this experiment is that it is not a representative model of how capacitors are mounted on the board in a real circuit. So the results are not representative. You need to (at least) include trace inductance, via inductance, model the source (regulator) and load (chip(s) ) as well in order to get valid results. The impedances are so low that the circuit board itself forms a component as well. So you can't leave the circuit board out. The creator of the video linked to in the first post fell into the same trap. As I wrote before: A PDN network looks more like a bunch of cascaded elliptic, low-pass LC filters. These filters are quite sensitive to component values and need proper input and output impedance matching.

Nominal Animal: It's an interesting experiment, and I saved it for future reference. Thanks for posting it.
nctnico: I fully agree with you. PDN is not a transmission line, you typically have an entire plane or split plane for a power supply. There will be distributed capacitance in the several pF region in, with the inductance of almost nothing.
Plus what might be a bigger issue is that there wasn't any DC applied to the capacitors.
Best is to test with the real device. Connect a power rail probe and a high speed scope, look at the noise in the time domain, look for dips that would violate minimum voltage specifications. And look with a FFT in frequency domain for typical noise figures, and how to get rid of them with the soldering iron. At least having several different size capacitors with different footprints give options.
Shoul dI even bring up ferrite beads? More oil on the flam?

[Siwastaja]

entire plane or split plane for a power supply. There will be distributed capacitance in the several pF region in, with the inductance of almost nothing.

Yeah. Power planes are another widely misunderstood things. You have it correctly here but the devils in the details: several pF (not more) with inductance of "almost nothing". This means just the vicinity of the power pin; only that power plane contributes. This is also why wide power tracks (think segmented plane) are as good as full planes. The further you go from the power pin, the more inductance - physical loop distance - you again have, the fact it's a plane doesn't make it any more magical.

You could model the plane as a transmission line, but then you would also need to magically couple to the component leg with the whole width of the plane. Not possible.

In other words, calculating plane capacitance for a full large PCB - resulting much larger number than a few pF - and then thinking that this is available to the IC power pin, is incorrect.

[nctnico]

Yep. Powerplanes or large copper sections are not a golden bullet. I've seen designs go wrong due to too high DC resistance or decoupling not being close to a pin. I'll admit that these where demanding designs though (high speed chips drawing several amps).

[thm_w]

This is the generic (simplified) concept: three impedance curves, each have same total C, each have same package size

Red: single large capacitor
Green: Multiple same capacitors with same total capacitance as red
Blue: Multiple different value capacitors with same total capacitance

lol, you could have used the image from link above:

Quote from the article:
Do not be lulled into thinking that three different values of capacitors is a robust strategy, or that three capacitors all the same value is more robust. Without a system level analysis, they both may be equally acceptable, equally marginal, or fail from the same faults.

Sure, so what they are likely saying is there are exceptions as well. But in the vast majority of cases, its done for no good reason, and performance would be better if you follow Bogatins recommendations instead, if you are not able or willing to do any analysis.

[Nominal Animal]

Best is to test with the real device. Connect a power rail probe and a high speed scope, look at the noise in the time domain, look for dips that would violate minimum voltage specifications. And look with a FFT in frequency domain for typical noise figures, and how to get rid of them with the soldering iron.

Oh, absolutely.  For an MCU, try to stress the core and the peripherals some, too, not just let it sit idle in reset.

But, what do you do in the schematic and design phase, when the only thing the IC datasheet says about power delivery and bypassing is "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible", for an IC with a 50 MHz clock, 5V supply, and a 3.3mA active current draw?

I would not trust that datasheet regardless of what nctnico says.  Instead, if I wasn't just a hobbyist but doing this stuff professionally, I'd do minimal test board(s), and measure as you described, and experiment with a few standard capacitor types (C0G/NP0 and X7R) and values (100nF to 4.7µF) in different sizes (preferably on separate boards, using standard/optimal footprints for each size), to see how the ripple and noise is affected; maybe make a second PCB based on the first especially if multiple caps are needed, then make an informed guess based on the measurements.  Testing would also show if one can get bitten by the parallel antiresonance peaks when using different-valued capacitors.

Are there other ways to go about it?  I do know of Fast Field Solvers that one can use to find the inductance and capacitance of conductor topologies, so if the datasheet or design mentions key frequencies, one could at least get into the ballpark, and compare different layouts to find out their properties (self-inductance in particular for IC decoupling capacitor loops).  But that's more like checking beforehand which kind of PCB layout might be most useful for the real-world testing.

[nctnico]

Best is to test with the real device. Connect a power rail probe and a high speed scope, look at the noise in the time domain, look for dips that would violate minimum voltage specifications. And look with a FFT in frequency domain for typical noise figures, and how to get rid of them with the soldering iron.

Oh, absolutely.  For an MCU, try to stress the core and the peripherals some, too, not just let it sit idle in reset.

But, what do you do in the schematic and design phase, when the only thing the IC datasheet says about power delivery and bypassing is "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible", for an IC with a 50 MHz clock, 5V supply, and a 3.3mA active current draw?

I would not trust that datasheet regardless of what nctnico says.

Well, that is not what I wrote exactly. What I wrote was that the manufacturer's information (datasheets, application notes, reference designs and support) is the first port of call. I looked at the reference design of the EFM8BB50 but that doesn't instill much confidence either. The project doesn't even have a decent bill-of-materials which is a red flag where it comes to the qualifications of the person who did the reference design. But this could be a generic Altium problem. I've seen other engineers struggling with getting a decent BOM from Altium.

So with the EFM8BB50 you are left with three options: ask Silabs what the deal is with decoupling. If that doesn't result in a satisfying answer, then either use a different part with complete specs or measure it yourself. Keep in mind that measuring it yourself takes time and pushes the engineering costs up making a different part, which has been properly specced, possibly cheaper to use.

Are there other ways to go about it?  I do know of Fast Field Solvers that one can use to find the inductance and capacitance of conductor topologies, so if the datasheet or design mentions key frequencies, one could at least get into the ballpark, and compare different layouts to find out their properties (self-inductance in particular for IC decoupling capacitor loops).  But that's more like checking beforehand which kind of PCB layout might be most useful for the real-world testing.

That is overkill as it would take very carefull setting up of the circuit board model. And after a cursory look it doesn't seem like that software is very useable as-is for PCB layouts. Higher end CAD packages have impedance simulations build in though and doing AC and DC PDN analysis are expensive extra options.

Doing DC analysis using open source tools is pretty tedious already. Robert Feranec published a video a few years ago:


However, it never hurts to play with a field solver like Sonnet lite. I have done some interesting simulations with it using lumped parts on microstripline circuits (filters in the 300MHz to 1GHz range). It certainly gives you a good understanding of how high frequencies interact with a board layout as Sonnect can plot the current densities in the board changing along with the frequency.

More hands on: you can follow the trial & error approach suggested by tszaboo; add places for extra capacitors to the design and measure the result. It is easier to not populate parts on a board compared to adding extra parts as a bodge. Having something like a Nano-VNA (lowest cost solution) could be useful but I don't know if the performance is decent enough in the 100kHz to 20MHz range. The articles I linked to earlier give a decent approach on how to determine the required decoupling capacitor if you start without any decoupling capacitors and do VNA measurements. For a relatively simple circuit consisting of a microcontrollers and some auxilary chips powered by the same supply, this should be doable.

[Siwastaja]

More hands on: you can follow the trial & error approach suggested by tszaboo; add places for extra capacitors to the design and measure the result. It is easier to not populate parts on a board compared to adding extra parts as a bodge.

Generally a good idea, but don't go overboard with this. If adding extra footprints compromises the layout otherwise, e.g. by moving capacitors out of best spots, or wasting area otherwise usable for more vias (e.g. two per footprint instead of one), then the cure was worse than the disease - and worse, cure was premature, often there is no disease. But sure, whenever adding extra footprints is relatively easy and with no compromise, do it.

For something like usual microcontrollers, just following the modern, well-understood best practices - one contiguous ground plane, 1uF 0402 bypassing as close as power pins as humanly possible; enough ground vias and stitching layers together - nearly guarantees EMC pass. Any EMC problems are going to be elsewhere. External interfaces, ESD, and so on. Maybe switch mode converters. An MCU fails immunity or emissions only if the layout or bypassing is seriously botched.

[Marco]

If embedded capacitance materials were to become multilayer, all the decoupling capacitors could go away.

As long as PCB manufacturing uses laser drilling and epoxy filling, I don't see why it couldn't be done. Laser drill the vias a little larger, epoxy fill the holes, then redrill the right size. You'll drill through some of the stitches keeping the capacitor stack properly connected, but those will be vastly redundant.

[TimFox]

"Muntzing" is a technique, dating back to vacuum-tube TV receivers, of removing components until the circuit stops working.
The original application was screen bypass capacitors at the tube sockets of the IF amplifiers, which could be snipped off in real time with an insulated pair of diagonal cutters.
Eliminating a screen bypass capacitor reduced the gain of that stage.
Peases's historical description:  https://www.electronicdesign.com/technologies/industrial/boards/article/21771148/whats-all-this-muntzing-stuff-anyhow

[nctnico]

More hands on: you can follow the trial & error approach suggested by tszaboo; add places for extra capacitors to the design and measure the result. It is easier to not populate parts on a board compared to adding extra parts as a bodge.

Generally a good idea, but don't go overboard with this. If adding extra footprints compromises the layout otherwise, e.g. by moving capacitors out of best spots, or wasting area otherwise usable for more vias (e.g. two per footprint instead of one), then the cure was worse than the disease - and worse, cure was premature, often there is no disease. But sure, whenever adding extra footprints is relatively easy and with no compromise, do it.

For something like usual microcontrollers, just following the modern, well-understood best practices - one contiguous ground plane, 1uF 0402 bypassing as close as power pins as humanly possible; enough ground vias and stitching layers together - nearly guarantees EMC pass. Any EMC problems are going to be elsewhere. External interfaces, ESD, and so on. Maybe switch mode converters. An MCU fails immunity or emissions only if the layout or bypassing is seriously botched.

IME, EMC is least of the concerns where it comes to proper decoupling. The primary function of decoupling is reducing ripple on the supply lines in order to reduce noise in sensitive analog circuits and to keep the supply voltage within tolerances so a device operates reliable. Sure, a poorly decoupled digital or HF circuit can be prone to emitting more radiation but the biggest problem is likely that it won't work very well.

[Nominal Animal]

But, what do you do in the schematic and design phase, when the only thing the IC datasheet says about power delivery and bypassing is "1 μF and 0.1 μF bypass capacitors required for the power pins placed as close to the pins as possible", for an IC with a 50 MHz clock, 5V supply, and a 3.3mA active current draw?

I would not trust that datasheet regardless of what nctnico says.

Well, that is not what I wrote exactly.

It is how I read your position, causing the argument.  You see, we are in full agreement that "the manufacturer's information (datasheets, application notes, reference designs and support) is the first port of call".  It definitely is!  The problem is that for many MCU's, the datasheets and so on are just as lacking as for SiLabs EFM8BB50. 

The disagreement happened because of your statements like "No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values." just do not match the quality of information in datasheets of many of the (cheaper end) microcontrollers I use and consider using, the EFM8BB50 just being a typical example.  Your statement definitely applies to e.g. Microchip PIC16F152 series datasheet (section 4, starting at PDF page 18), which describes the PDN in quite useful detail with practical advice and guidance easy to understand even for a hobbyist; but in my experience, among the cheaper microcontrollers, it is a rare good example, and not the norm at all.

Are there other ways to go about it?  I do know of Fast Field Solvers that one can use to find the inductance and capacitance of conductor topologies [...]

That is overkill as it would take very carefull setting up of the circuit board model.

True, although I do suspect it would be possible to do a KiCad plug-in to export the PCB gerbers and vias — the basic geometry, in other words —, but the IC part (including legs for SMD and TH packages) would be simplified to a jumper wire.  For comparative testing of options that would suffice, but it would not have any predictive power wrt. coupled, conducted, or radiated EMI.  The reason I mention Fast Field Solvers, is because I have an extensive simulator development background, prefer using Open Source because of being just a hobbyist and having no budget to spare (but not ideologically opposed at all, even though Tux is my mascot), and this kind of stuff is much more familiar to me than EDA or CAD software, especially the high-end professional EDA/CAD stuff.

Higher end CAD packages have impedance simulations build in though and doing AC and DC PDN analysis are expensive extra options.

Ah, I didn't realize.  I should have expected that.

I also haven't used the E. M. Workbench, the FreeCAD-based interface to some of the Fast Field Solvers, yet.

For a relatively simple circuit consisting of a microcontrollers and some auxilary chips powered by the same supply, [practical experimentation along the lines tszaboo described] should be doable.

Absolutely, and for the small microcontrollers with poor documentation, also cheap enough even with a few test/experimental PCBs, as long as one has a decent (not that expensive) network analyzer, or even an oscilloscope with careful measurements (x1 probing for ripple/spectrum, x10 for noise/peaks) undestanding the effect of the probe capacitance, inductance, and input impedance.

All this just leads to one being very suspicious when first looking up a possible new MCU one might want to use.  Again, the MCUs with poorly documented and likely un-characterized PDNs do seem to mostly rely on cargo-cult throw these capacitors at it and it'll be golden "design principle", which easily leads hobbyists astray, and may even become an attitude one does not even notice enough to question... so even for hobbyists, knowing how to verify and do it better, would definitely be useful.