Decoupling capacitors and perceived wisdom

[Siwastaja]

Finally, the circuit does not understand what is called "ground" - so the loop area matters.

By "ground", I was referring to the potential at the so-called GND pin on that IC, and at the power supply return, nothing more.

As long as the other end of the capacitor has that same potential, and it does not vary at short timescales, no current flows in or out of the capacitor end at that potential.  The capacitor is not part of a current loop — no current flows across the capacitor, only across the end that has a varying potential on it —, so why would the area of some loop dictated by the capacitor be significant?  Other than as a source for coupled noise from elsewhere, that is.

But of course current flows through the capacitor. Otherwise it would be unnecessary. The whole purpose of the capacitor is that it can supply the current peaks the IC needs quickly, with least amount of inductance slowing down dI/dt.

And because current flows, potentials (measured between any two points) change. We try to minimize that potential change, by minimizing impedance. Yes, this means that even the ground plane is not at equal potential.

[Nominal Animal]

But of course current flows through the capacitor.

No.  A capacitor stores charge; the movement of charges is the current; and the cause for the movement of charges is a change in the potential.

In a very real, very physically exact sense, the current enters or exits the (multilayer) capacitor on the end where the voltage potential varies.  The current flow is dictated by the time derivative of the voltage potential across the whole capacitor.  When one end of a capacitor is held at a constant potential — constant meaning no change in the kind of short intervals we are talking about — there is no current flowing to or from that end of the capacitor.

Edit: Someone with the test equipment needed could test this in practice, by using two current-sense resistors before and after a capacitor, and a single-ended signal generator connected to one end, the other end to the common "0V" or "GND" reference potential, and some (much larger) load resistor in parallel with the resistor-capacitor-resistor assembly.  You should see the signal only on the sense resistor directly connected to the signal generator, with the voltage on the sense resistor on the other side of the capacitor being basically the "0V" reference potential.  I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself.  Practice always trumps theory.

[Nominal Animal]

Let me reply to myself.

Electrically, an ideal capacitor is modeled as passing current \$I = C \frac{d \, V(t)}{d \, t}\$ (through both ends of the capacitor), i.e. directly proportional to the rate of change of the voltage across the capacitor.  Physically, this is indeed best modeled as charges passing through both ends of the capacitor.

So, me claiming that no current passes on the other end of the capacitor is utter bullshit.

The current that passes on either ends of the capacitor is the same: the difference between the current drawn by the IC, and the current draw seen by the supply.  The capacitance is not actually a constant, but depends on the voltage, and the inductance (or impedance, rather) of the circuit it forms with the IC.  To maximize the effective capacitance, one usually needs to minimize the inductance.  For a simple conductor, the loop area is the simplest approximation to its self-inductance.  This is what leads to the rule of minimizing IC-and-capacitor loop area to maximize capacitor effectiveness in keeping the IC supply voltage stable.

[Someone]

I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself.  Practice always trumps theory.

A capacitor is a two terminal device, current must flow through it for it to have any effect at all. As Siwastaja says, if there is no current interacting with the capacitor it can be removed with no effect.

[nctnico]

At the moment I'm looking at an FPGA for a high speed design. In the hardware design manual, the manufacturer is very specific about the decoupling capacitors to use:





This is not by chance or rule-of-thumb. These values have been obtained by analysis of the chip, package and circuit board layout. So if you adhere to the design guidelines and power supply routing examples, you'll very likely end up with a design which is pretty close to optimal given the design constraints.

FPGAs are one of the most well documented parts for this purpose, because designing with these parts depends a lot on the chip floorplan and switching activity. Some customers will need to be able to verify their own custom design.
If you want to get any accurate power figures of a modern FPGA, you basically need to have your core design finished, with switching activity stimulus supplied, and only with this information a proprietary tool will spit out the most accurate figures of power supply requirements. Indeed, there is no rule of thumb, but there is also no omniscient appnote that will do this work for you.

The datasheet for this PolarFire FPGA specifically says:

Decoupling capacitors other than those listed in the previous tables can be used if the physical sizes of capacitors meet or exceed the performance of the network given in this example. Substitution would require analyzing the resulting power distribution system's impedance versus frequency to ensure that no resonant impedance spikes the result. See Figure 1-1 for power supply design.

Or in other words: exceed these specs, verify substitutions. The 2nd table from your list is described as "Recommended Decoupling Capacitors For PolarFire Devices". There are still some values missing, which means that all designs require some amount of substitution or eyeballing, still.

Sorry, but I don't see where the values are missing. They list 10 capacitors in the placement table and 10 capacitors in the parts table. When there is no number in the placement table, the value is not to be used. There are more tables where different parts are used depending on package size (and PCB width / distance parameters).

Other chips may not be so well off. There are also plenty of appnotes out there for MCUs, MPUs, etc. that use the "100nF on every VDD" whilst supplying no information about the on-chip decoupling measures, the ripple specifications, layout, etc. Yet still the processor is switching at the best part of a GHz and comes in a LQFP-64 package I could even shove into a breadboard when I solder it to an universal breakout board (bad idea).

Most if not all modern (high speed) microcontrollers have internal regulators. So the sensitive power integrity is handled inside the package entirely. The I/O section is about the only functional group powered by the external supply. This makes the decoupling requirements not so strict which is good as many microcontrollers end up on 2 layer or even single layer boards.

[mawyatt]

Most if not all modern (high speed) microcontrollers have internal regulators. So the sensitive power integrity is handled inside the package entirely. The I/O section is about the only functional group powered by the external supply. This makes the decoupling requirements not so strict which is good as many microcontrollers end up on 2 layer or even single layer boards.

Back in the days when we were still involved in IC design, the SoC chips were designed with distributed LDO regulators scattered throughout the chip to help with the internal on-chip PDN. These LDOs were designed with specific external capacitors at specific electrical distances to the external voltages and grounds. We even developed and patented (7728565, Non-Invasive Load Current Sensing in LDO) special on-chip LDOs that allowed internal/external dynamic IC load monitoring without introducing any effects on the LDO or load. For special noise sensitive functions such as on-chip VCOs, Amplifiers, and DLLs which require low supply noise, we developed and patented a special Low Noise LDO (8692529) which had a unique architecture for noise decoupling based upon a Super-Source-Follower (BTW Intel copied/independently (?) developed this....long story discovered at ISSCC a decade ago).

Best

[SiliconWizard]

I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself.  Practice always trumps theory.

A capacitor is a two terminal device, current must flow through it for it to have any effect at all. As Siwastaja says, if there is no current interacting with the capacitor it can be removed with no effect.

Ah, this is one of these tricky matters. Dave actually talked about it in a now old video:



For the practical purpose of designing electronic circuits, the subtlety usually doesn't matter too much, but it's still an interesting point.

In a related vein, you can also have a look at this long thread: https://www.eevblog.com/forum/chat/veritasium-(yt)-the-big-misconception-about-electricity/

[jnk0le]

So, when the vendor says:

Recommendation of 0.1 μF (100 nF), in parallel with a 1000 pF (1
nF), 10-20V. These capacitors should be low-ESR and have a resonance frequency in the range of
20 MHz and higher. Ceramic capacitors are recommended.

If the board is experiencing high-frequency noise above tens of
MHz, add an additional ceramic-type capacitor in parallel to the decoupling capacitors. The value
can be in the range of 0.01 μF to 0.001 μF. Place this capacitor next to the primary decoupling
capacitors. In high-speed circuit designs, consider implementing a set of capacitances as close to
the power and ground pins as possible. For example, 0.1 μF in parallel with 0.01 μF and 0.001 μF.

It's best to ignore it, and use one larger cap instead. (or 2x 100n)
Because those smaller caps are only increasing the noise.

[nctnico]

No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values. Without measuring, you can't say what using different values will do.

[Nominal Animal]

In case anyone wonders about it, I was applying the electrostatic model — as in, what happens when you have two isolated charged conductors and bring them to contact — to decoupling capacitors.  The no-current part is based on perfect dielectric model.  It is not at all what happens when a capacitor is part of an electrical circuit (and indeed the links SiliconWizard included discuss the correct model).

It is a good example of what happens when you apply the wrong physical model to the situation.  (Extremely embarrassing to me, sure, but it happens.)

No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design

The obvious errors found in datasheets indicates "very likely have done" is quite optimistic.  It may be so in some specific manufacturers' specific product lines, but I'm much less convinced it is true in general.  For many cheaper microcontrollers, decoupling capacitor recommendations seem to be based on some random engineer saying "I tried 100nF and it seems to work, so let's recommend that in the datasheet".

For things like DC-DC switchmode controllers, I'm sure the supply decoupling is much more carefully investigated, and one should not ignore manufacturer recommendations.  Some datasheet even contain tables listing various combinations of decoupling capacitor values and inductor values, with manufacturer recommedation "grading" (IIRC, TI uses "++", "+", and empty for not recommended).

[Someone]

I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself.  Practice always trumps theory.

A capacitor is a two terminal device, current must flow through it for it to have any effect at all. As Siwastaja says, if there is no current interacting with the capacitor it can be removed with no effect.

Ah, this is one of these tricky matters. Dave actually talked about it in a now old video:

For the practical purpose of designing electronic circuits, the subtlety usually doesn't matter too much, but it's still an interesting point.

In a related vein, you can also have a look at this long thread: https://www.eevblog.com/forum/chat/veritasium-(yt)-the-big-misconception-about-electricity/

okay you can do all your electronics simulations and understanding through FEM and field solvers. The practical models that are used successfully for the majority of circuits (including RF) are two terminal and do not include any of those effects.

PS linking to a video as an explanation without saying what in it is supporting in your claim is a waste of everyones time.

If a capacitor did not have current passing through it, then it could be removed without any effect. Still applies even in the EM field solutions. So you’ve only added noise and confusion.

[Someone]

In case anyone wonders about it, I was applying the electrostatic model — as in, what happens when you have two isolated charged conductors and bring them to contact — to decoupling capacitors.  The no-current part is based on perfect dielectric model.  It is not at all what happens when a capacitor is part of an electrical circuit (and indeed the links SiliconWizard included discuss the correct model).

Current cannot enter and exit a single terminal without an equal and opposite current appearing elsewhere. You’d be throwing away the basic underlying assumptions of field or lumped models. The free energy nut recently trying to claim otherwise was roundly laughed at for trying to say they had a way around all currents are continuous loops summing to zero.

There are no clever word games or reframing to fix that. Your use of the term current is fundamentally wrong.

[TimFox]

In circuits with capacitors, there is "displacement current" inside the ideal capacitor, and "conduction current" in the two leads.
Displacement current is a feature of the polarization within the capacitor, which gives the capacitor more capacitance than an equal geometry with vacuum between the plates.
This is similar to the increase of inductance when a permeable material (paramagnetic or ferromagnetic), capable of magnetic polarization, is introduced into the coil.

[Nominal Animal]

Current cannot enter and exit a single terminal without an equal and opposite current appearing elsewhere.

Only if you are talking about an electric circuit, in the context where Kirchhoff's current law applies.  Physically, current is just the rate of net charge flowing through some cross section.

Consider an ESD event, for example.  Say, two hollow conductive spheres in vacuum with different charges coming into contact.
At the contact point a current will flow until the charge density across the entire conductive surface has equalized.  There is only this single current.

For electric and electronic circuits, we apply a different model to describe systems involving non-static electricity, specifically Kirchhoff's circuit laws.  To remind everyone,

• The algebraic sum of currents in a network of conductors meeting at a point is zero.
• The directed sum of the potential differences (voltages) around any closed loop is zero.

These only apply to circuits (and not to e.g. ESD events), and at frequencies where the wavelength is much longer than the circuit length.  Beyond that, one has to go directly to Maxwell–Heaviside equations describing classical electromagnetism.  To properly describe transmission lines, we apply telegrapher's equations (transmission line model); and at even higher frequencies, waveguides (again based on Maxwell–Heaviside equations).

Your use of the term current is fundamentally wrong.

If you look at any physics textbook or even the Art of Electronics, you'll see they use "current" with the exact same definition I have.

I used the wrong model and approach, the electrostatic one, instead of electric circuit models.  Yes, that was stupid of me, and a fundamental error, but one of applying the wrong model to the problem at hand, not a "clever word game" or "reframing".

[Someone]

I used the wrong model and approach, the electrostatic one, instead of electric circuit models.  Yes, that was stupid of me, and a fundamental error, but one of applying the wrong model to the problem at hand, not a "clever word game" or "reframing".

Thread is talking about practical capacitors and how to select/use them. Trying to walk off into mental games of superconducting ideal conductors in lossless voids is reframing (after the fact, it was never clear) and trying to be “clever”.

You claimed this was practical in your opening arguments:

Edit: Someone with the test equipment needed could test this in practice, by using two current-sense resistors before and after a capacitor, and a single-ended signal generator connected to one end, the other end to the common "0V" or "GND" reference potential, and some (much larger) load resistor in parallel with the resistor-capacitor-resistor assembly.  You should see the signal only on the sense resistor directly connected to the signal generator, with the voltage on the sense resistor on the other side of the capacitor being basically the "0V" reference potential.  I fully admit I could have the physics of capacitors wrong, being unable to verify this in practice for myself.  Practice always trumps theory.

We have righty pointed out this is incorrect by using clear arguments falsifying your claims. But instead its now reframed as “but but but in some other context which was never mentioned previously the concept could technically be correct in some abstract way”. Thats word games.

Currents have to flow in zero sum circulation. Basic underlying physical laws. They cannot appear in isolation.

Lets go with an Oxford definition of electrostatic:

relating to stationary electric charges or fields as opposed to electric currents

There is no current in an electrostatic model! Perhaps keep redefining things until you randomly find something which is true? You sound like the free energy nuts at this point.

[Nominal Animal]

We have righty pointed out this is incorrect by using clear arguments falsifying your claims.

You obviously missed me pointing out I was wrong in #52.  Perhaps the concept of someone admitting they were wrong before anyone else noticed or commented on it is utterly alien to you?

[Someone]

We have righty pointed out this is incorrect by using clear arguments falsifying your claims.

You obviously missed me pointing out I was wrong in #52.  Perhaps the concept of someone admitting they were wrong before anyone else noticed or commented on it is utterly alien to you?

But you’re still arguing something something something wall of text ? ? ?
ESD and lightning discharges do have a closed loop of current.

[Nominal Animal]

But you’re still arguing something something something wall of text ? ? ?

Just add me to your ignore list, please.  It's not like you ever contribute anything useful anyway.

ESD and lightning discharges do have a closed loop of current.

Nope.

[ejeffrey]

And I still haven't gotten a single reply on whether it suffices to minimize the VCC-to-bypass capacitor distance, or whether one should consider the bypass-to-ground distance also, in practice.

What you  are about is the whole loop, so the Vcc and ground leads to the capacitor are equally important. For high frequency the capacitor itself might as well be a solid block of metal.

The details depend a bit on your pcb stack up.  For high density boards with thin dielectric, the plane inductance is tiny.  So you just want get down to the power/ground planes as quickly as possible.  If you can use via in pad that keeps the loop area the smallest.  If that doesn't work, put the vias as close as possible and to the side of the capacitor rather than above and below.  Once you have food via placement for both the component leads and the bypass capacitor the location of the bypass capacitor itself hardly matters.

For something like a 4 or 6 layer board the plane inductance might be higher so you want to try to keep the bypass capacitors closer to the power pins.

[ejeffrey]

But of course current flows through the capacitor.

No.  A capacitor stores charge; the movement of charges is the current; and the cause for the movement of charges is a change in the potential.

For the purposes of electronic circuit design you can essentially 100% of the time consider only the total current as the coulomb current plus the displacement current.  In that case "current always flows in loops" is an iron clad law of nature, and it's always true not just on average but at every instant. You are of course free to not do this, and only define free charge movement as "current" but you are making your life unnecessarily difficult, and for no real benefit.

In this mode of analysis it's correct to say current flows through the capacitor.  This works really well with lumped element circuit models (although it is far more general than that).  If you have a current imbalance, say more charge entering the left plate than leaving the right, that creates a net charge and therefore an electric field.  Those electric field lines have to go somewhere, usually to the nearest ground plane.  Electric field between two metal conductors is just a capacitor. So now we turn the problem of handling unbalanced current flow into a realizing that it's just a parasitic capacitance.

[Siwastaja]

They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values.

You wish 

Some may have. In reality, example circuits are usually just "good enough". Heck, it is completely normal that application examples are not even working properly.

So, when the vendor says:

Recommendation of 0.1 μF (100 nF), in parallel with a 1000 pF (1
nF), 10-20V. These capacitors should be low-ESR and have a resonance frequency in the range of
20 MHz and higher. Ceramic capacitors are recommended.

I would ignore it by default, and adjust if necessary.

I don't think it is that common to accidentally cause serious enough resonances to make this "2-3 different capacitor values" concept perform significantly worse. It is still nevertheless a stupid thing to do by default: it increases your BOM cost and is not useful. Unless you count "following manufacturer recommendation" as a positive. It might be, depending on how bureaucratic your organization is, and how much trust is placed on you as an engineer.

This whole capacitor thing is typical example of cargo cult. Those capacitors are placed and recommended because others have done it. And it works, just like adding a capacitor made of cardboard works. When the designs work and pass, it is easy to keep recommending. This is also why we need a little bit of courage of stop doing that.

[tggzzz]

They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values.

You wish 

Some may have. In reality, example circuits are usually just "good enough". Heck, it is completely normal that application examples are not even working properly.

As with everything, you have to judge why the information was produced. I was once asked to create digital logic simulation models, and the client didn't want to think about acceptance tests. They just wanted the be able to present them as a "yes we have it" tickbox to their clients. I declined their money

For bog-standard opamp circuits they may well not have tested the schematic.

For RF circuits where the datasheet or application notes contain a schematic and PCB layout, something close to that has probably been tested.

For RF and complex digital evaluation boards with schematics and PCB layout, it is wise to pay very careful attention.

[nctnico]

They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values.

This whole capacitor thing is typical example of cargo cult.

Where is your evidence? And don't point to the video linked to in the first post. It is a school book example of simplifying a model to the point where it is completely wrong.

All of the designs I did with high speed parts where it is clear that the manufacturer did PDN simulation and testing, end up using different values. None of the materials written by real experts I have come across state that using single or different values is always right or wrong. Those materials only say: simulate & measure (which makes most sense to me). IOW: you can't go around and claiming to ignore manufacturer recommendations as a general advice as you can't know whether your suggestion is an improvement or makes things worse.

[Howardlong]

They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design and that resulted in the recommended values.

You wish 

Some may have. In reality, example circuits are usually just "good enough". Heck, it is completely normal that application examples are not even working properly.

While this may well be the case, good luck getting meaningful vendor support if you drift away from their published recommendations!

I'm with @nctnico on this, the first port of call is the vendor's own datasheet recommendations and published reference designs IMHO. And yes, the datasheet recommendations and reference designs do often differ, in which case probably the reference design is the starting point.

[nctnico]

No, do NOT ignore the manufacturer's recommendation. They very likely have done extensive simulations and testing to optimise power integrity as part of the chip design

The obvious errors found in datasheets indicates "very likely have done" is quite optimistic.  It may be so in some specific manufacturers' specific product lines, but I'm much less convinced it is true in general.  For many cheaper microcontrollers, decoupling capacitor recommendations seem to be based on some random engineer saying "I tried 100nF and it seems to work, so let's recommend that in the datasheet".

And how do you get to the conclusion it is random? I can understand that 100nf looks like a historically grown standard without much merit. But you also need to consider that because 100nf is standard for decoupling capacitors, chips might be designed specifically to have a 100nf decoupling capacitor externally. But these are still assumptions. Usually there is a lot more information to be found beyond the datasheet. For starters in the application notes and many manufacturers have support staff which helps to answer more in depth questions.