Electronics > FPGA

Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...

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I am finishing my small CPLD development board and finaly got some testing to do. I have made a simple 4bit counter in VHDL, clocked by a GCLK2 pin. But it doesn't work at all. With clocks on GCLK1, the counter runs fine.

The board provides two clocks to the CPLD:  GCLK1 is 2048Hz, GCLK2 is 2Hz. Both signals are present directly on the chip pins (verified with scope, many times).

Why doesn't my design work with pin 40 (GCLK2) as a clock input?

I see that the GCLK2 pin is also shared with anothe dedicated function (OE2). Have I missed some settings in Quartus?

Sorry for such stupid questions, I am only a programmable logic greenhorn.

Thank you,

A small update:

As the only pins I have free on the CPLD are 38 (OE1) and 39 (GCLRN), I have tried connecting those to the 2Hz clock right there.

Guess what! It works, no issues clocking from these pins.  Why the hell is pin 40 (OE2/GLCK2) not working?


The hell why also pin 42 does not work?

Forget that, the device gets replaced.

You're right of course. But I'm trying to absorb some basic knowledge of programmable logic. So it is a good practice to learn what should be connected where. And it wasn't so much of a trouble at the PCB design stage to connect the clocks to the right pins, so I left the clocks where they should be, in a potentialy fast clocked application.

Note: So low clock frequency was chosen due to the fact the CPLD is very small (64 macrocells), so there is not much space for long clock dividers if someone wants to make a counter with human-recognizable output on my CPLD kit.

I have replaced the chip and the issue has gone. So a success. You can scrap this thread, useless.

When I found another pin (or maybe pins?) behaving strange, I knew the device must be faulty. (At the stage I knew only the pin 40 (GCLK2/OE2) hasn't been working, I thought there might be some issue with incorrect "settings" somewhere in the project, hence my stupid question)


After playing with the PLD a while, I have found just other issue with the new chip. When using macrocells near pins 8, 13 or 15 it even fails to program it. Otherwise the device works fine.


Those devices are a load of horseshit. (or I got a load of horseshit)

Let's try soldering another one and see what happens.

Sounds more like you forgot some of the power/ground pins or a pin which needs a pull-up / pull-down doesn't have one.


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