Altera MAX 10 accessing lpddr2 sdram

[pinout_1]

Hello. I'm fairly new in FPGA, but I got a task to access LPDDR2 SDRAM memory based on the MAX 10 10M50 FPGA Evaluation Kit. So, sorry for my misunderstanding, but maybe you can point me to the right direction.  I have been able to program the board for simple on-board led blinking, but even with a large amount of documentation, I still can't access the memory. I use Quartus prime Lite with Quartus Prime programmer. I need to generate a video output signal and write data into the onboard LPDDR2 SDRAM memory. When I can access the memory, then I think I can try to test HDMI video framing.

Thanks for the answers

[Jope]

You can use the UniPHY IP core from Altera/Intel.

[Daixiwen]

Did you have a look at the design example for your kit?

[Scrts]

There are more relevant examples as well: https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/framebuffer-driven-lcd-display/

You will most likely need Nios (at least free version) to initialize the memory and the registers.

Before you include frame buffer, try to generate video frames using a color bar generator and video output block. It will not need Nios or frame buffer to get the actual video on the display.