capture data from ADC with ISERDESE not working

[VAO1]

Good day.
I need to acquire the data coming from an 12 bit ADC, which has 8 LVDS outputs, one frame clock, and one bit clock. To do this, I am basing the design in the XAPP524 document from Xilinx. To do this, first I am deserialising the frame clock using an ISERDESE2. For this deserialization, the ISERDESE uses as input the positive part of the frame clock, as CLK clock the bit clock, and  as CLDIV clock an aligned version of the frame clock with the bit clock (As stated in document UG471), also it has a bitslip signal, but not using that yet.
The problem is that the output of the ISERDESE2 keeps changing, but the signal being input to it is allways the same, and dont really now why this is.
I attach a picture of the waveforms, where i_rst is the reset signal, I-ADCLK_94_p_0 is the input signal (to D pin in ISERDESE), LCLK is the bit clock, adclk is the aligned with bit clock version of the frame clock (input to CLKDIV of Iserdese) and frame_para_odd[7:0] is the output of the ISERDESE.
 
Any help would be apreciated, because dont really now why this is hapening.
Thanks a lot in advance.

[Rainwater]

Is adclk suppose to be 50% duty cycle b/c it is 4high 3 low

[langwadt]

which ADC?

[VAO1]

Good day, Thank you for your answers
The ADC corresponds to the ADS5294. Its 4 up and 3 down because of the datasheet waveform (its 14 bits, I attach a picture).
Also, for the frame discovery machine (to synchronize the incoming data with the FPGA), I do not really understand how does it work. I have a code thats working (that was passed to me), but dont really understand how does it work (I also attach the code and the part of the code (ISERDESE) that makes the frame alignment). This works with a 12 bit word, so how could this be changed for a 14 bit word??, just changing the D value in the ISERDESE??
Thanks a lot in advance.

[Rainwater]

I haven't checked all the timing diagrams, but the one you posted and several others in the datasheet show the clocks out of phase with each other. Your trace is difficult to see, but looks as tho the clocks are in phase. The reoccurring data pattern is very strange comming from a real device. If the values where approximately the same, it would make sense, but being so different and repeating, it's either interlaced data or an accumulated error rolling over.

[VAO1]

Yes, they are out of face coming from the ADC, but they must be aligned for entering the ISERDESE. That is why they are aligned inthe code. I attach a picture of the not aligned (blue) and aligned (green) signals. Yes they where rolling, because that signal is for the 14 bit ADC, and the ISERDESE input was with 6 bits (haslf of a 12 bit signal). Now what I do not understand really is how does a frame alignment algorythm works. I posted one that was passed to me, but cant really understand how it works. I understand there is a frame pattern, that when its meet, you can start sampling the iinput with no problem, but dont really get how it works. Any hint in this would be apreciated,maybe a reference where I could read about this (the implementation of it).
Thanks a lot for the answers

[VAO1]

Good day,
starting from the beggining, the functioning of the ISERDESE. There is a thing I do not understand (maybe that should have been the first question). I have done a small program to just test the functioning of the ISERDESE. This progream just have an ISERDESE with the following definition:

Code: [Select]


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;
entity Prueba_ISERDESE is
  Port (
  test_signal      : in std_logic;  --- señal para prueba del ISERDESE
  i_ADclk_p        : in std_logic;
  i_ADclk_n        : in std_logic;
  i_Lclk_p         : in std_logic;
  i_Lclk_n         : in std_logic;
  i_rst            : in std_logic; 
  salida : out std_logic_vector (7 downto 0)
  ); 
end Prueba_ISERDESE;

architecture Prueba_ISERDESE of Prueba_ISERDESE is

signal adclk_i : std_logic;
signal lclk_sys : std_logic;
signal not_lclk_sys : std_logic;
signal Lclk : std_logic;
signal Lclk_B : std_logic;
signal adclk : std_logic;

begin
    Lclk <= i_Lclk_p;
    Lclk_B <= i_Lclk_n;   
process (Lclk)
    begin
      if rising_edge(Lclk) then
          adclk <= i_ADclk_p;
      end if;
    end process;
-------------------------------   
bufio_lclk_sys : BUFIO port map (I => Lclk, O => lclk_sys) ;
not_lclk_sys <= not(lclk_sys);
------------------------------
bufr_ad_n : BUFR generic map(BUFR_DIVIDE => "1", SIM_DEVICE => "7SERIES") port map (I =>  (adclk), CE => '1',O => adclk_i,CLR => '0') ;   
-------------------------------   
iserdes_frame : ISERDESE2 generic map(
  DATA_WIDTH         => 7,                      --- 7
  DATA_RATE          => "SDR",     
  SERDES_MODE        => "MASTER",     
  --IOBDELAY        => "IFD",
  DYN_CLK_INV_EN    => "TRUE",             
  DYN_CLKDIV_INV_EN    => "FALSE",   
  INTERFACE_TYPE     => "NETWORKING")   
port map (                     
  D           => test_signal,                 
  DDLY         => '0',
  CE1         => '1',
  CE2         => '1',
  CLK         => lclk_sys,
  CLKB        => not_lclk_sys,
  RST         => i_rst,
  CLKDIV      => adclk_i,
  CLKDIVP      => '0',
  OCLK        => '0',
  OCLKB        => '0',
  DYNCLKSEL        => '0',
  DYNCLKDIVSEL      => '0',
  SHIFTIN1     => '0',
  SHIFTIN2     => '0',
  BITSLIP     => '0',                         
  O       => open,
  Q8        => salida(7),
  Q7        => salida(6),
  Q6        => salida(5),
  Q5        => salida(4),
  Q4        => salida(3),
  Q3        => salida(2),
  Q2        => salida(1),
  Q1        => salida(0),
  OFB       => '0',
  SHIFTOUT1    => open,
  SHIFTOUT2     => open);

end Prueba_ISERDESE;
The waveforms of this is in the attached picture.
As I understand, the output from the ISERDESE happens in the next rising edge of CLKDIV, but in the attached picture, it is happening in 2 "stages", first bits 0 and 2, and then the rest of the bits. Also, because of the definition (DATA_WIDTH = 7), shouldnt the bit 0 be neglected (because the ISERDES fills first the Q( 8 ) output).
Thanks a lot in advance.

[Rainwater]

Thanks for the code tags.
 your trace do not show all the clocks and from other forms, the most approved solution has beed a proper phase relationship between them. Some chips even requiring a calibration period.
Maybe try setting the testbench to slowly alter the phase until the traces match the datasheet?
Another possibility 8s the data may need to be encoded with 8B/10B or similar. Im just a beginner myself, good luck

[nctnico]

Maybe this is a simulation issue. I see the inverted clock is being made from an assignment / equation. Some simulators don't look at a signal until the next transistion of the source signal and thus cause a delay of 1 clock cycle. To take this effect out of the equation, make all clocks in the test bench and don't have any assignments from one clock signal to another where it comes to clocks at any place in the code.

From my experience with GHDL this won't work properly when simulated:

Code: [Select]

Lclk <= i_Lclk_p;
Lclk_B <= i_Lclk_n;   
not_lclk_sys <= not(lclk_sys);