Author Topic: Creating a simple testbench  (Read 341 times)

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Offline Digitalio

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  • Country: mx
Creating a simple testbench
« on: May 27, 2020, 05:45:40 pm »
My current attempt to create a testbench for a led blinker module:
Code: [Select]
`timescale 1ns / 100ps

module Clock();

reg sysclk = 0;

initial begin
    forever begin
        #10 sysclk = ~sysclk;
    end
end

LedTest ledTest(sysclk, led_0);
 
endmodule

Am I doing it properly?
 

Offline ale500

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  • Posts: 352
Re: Creating a simple testbench
« Reply #1 on: May 28, 2020, 08:03:28 pm »
It should create a clock with a period of 20 ns. But what is led_0 ?

Without knowing what led blink does and what led_0 is, it may be enough or not.
The idea of the testbench is to exercise the logic, the fsm and so on. To try corner cases. To see if the given module does what you think it does :), it can do more too.

I'd recommend you always define all your signals. You can also use following directive
`default_nettype none

to force undefined signals to not have a default "wire [0:0]" definition, it helps finding some mistakes, specially when you forgot that the wire may need to be wider than 1 bit !.
 
The following users thanked this post: Digitalio

Offline Digitalio

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  • Country: mx
Re: Creating a simple testbench
« Reply #2 on: May 28, 2020, 08:47:08 pm »
I'd recommend you always define all your signals. You can also use following directive
`default_nettype none
Thanks, good idea. Strangely, with this directive on Vivado shows a hint in the editor, but still compiles the code without any warning. I wonder if it's possible to make it fail synthesis in this case?
 

Offline Dmeads

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  • Posts: 115
Re: Creating a simple testbench
« Reply #3 on: June 13, 2020, 05:00:28 am »
Try this?

:)

Code: [Select]
`timescale 1ns / 100ps
`default_nettype none

module Clock;
reg sysclk;  // you got the input right
wire led_0;      // the outputs from your LedTest module need to be listed as wires

always #10 sysclk = ~sysclk;  // exactly the same as "forever," just less words :)

LedTest uut(sysclk, led_0);  // the uut stands for Unit Under Test, and can just help you keep track of which module you're simulating

initial
begin
sysclk = 0;  // intialize sysclk to 0 just like you did, just in a different place
#200  // how many nanoseconds you want the sim to run, if want to run for 1000ns, change to "#1000"
$finish;  // tell simulator to finish
end  // end initial
endmodule  // Clock
 


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