I do not know about Xilinx specifics, but, remember in earlier discussion, if you make a clk_90 degree output, remember that a 270 degree is actually the same as !clk_90.
Also, according to the Xilinx data sheet, if you make a PLL output with clk_0, clk_90, clk_270, you can tie any of these outputs to one or two of that PLL's DCM modules and use that DCM to output 1 tunable 256 step phase from the clock you are receiving from the PLL. Also, the output from that DCM inverted will be 180 degree out phase compared to where you tuned.
Presetting and using multiple outputs from each DCM, or trying to get the DCM to do a frequency conversion will probably loose it's ability to be software tuned in real time. Since you get 2 DCM per PLL, and the PLL itself is also tunable, only with far fewer steps, your options should be almost boundless. This is why the main PLL should first be used for the main frequency conversion and system clock generation unless you are doing something special.