Well, the ifdef in circuit will be ignored is not selected.
The modelsim which came with altera knows how to properly simulated altera IP like it's ALTPLL and DDRIO. If you select CycloneIV as an FPGA, it can be setup to simulate with actual true IO timing.
Have you tried changing which default Verilog version Quartus uses?
In 'Assignment Settings / Compiler Settings / Verilog HDL Input', you may choose:
Verilog 1995
Verilog 2005
SystemVerilog
If this does work, it will not tell you what you have done which made your code not work with for example 'Verilog 1995'. (Well maybe you will see a 'warning' in the system messages window during compile which might offer a better clue.) It will be then up to you whether you want to further hunt down the issue.
Warning about Cyclone IV/V and Max10, they use different types of DDR ip and Quartus may compile Cyclone's DDR ip when generating a Max10 FPGA, but, it will not work on silicon and there is no warning. I did complain on Intel's forum, but not much came of it.