Efinix Efinity 2026.1 released

[Wiljan]

Efinix has released Efinity 2026.1

What I find interesting is the Efinity Partition Planner and the faster compile

New in v2026.1
The Efinity software v2026.1 has the following new features and enhancements:

Introduces support for Ti125 and Ti95 devices:
Supports enhanced I/O performance and power with the HSIO2 pins
Up to 2.5 Gbps MIPI RX/TX performance, and significantly lower power consumption for MIPI HS-RX (compared to HSIO)
Up to 1.8 Gbps LVDS RX/TX performance
All devices now require only 8 GB of memory
New PHY periphery clock network and distributed clock modifier (CM) resources optimize usage of PLLs and core clock network resources, provide easier peripheral clock skew management, and support higher performance
New device and package combinations include:
Ti125 and Ti95 in F225 packages, supporting easy migration from existing Ti60 and Ti35 F225 designs
Ti125M225S4F4, with in-package SPI flash memory and two HyperRAM devices in a small package footprint
Ti125 and Ti95 in F324 packages, with more HSIO2, HSIO, HVIO pins
Enables bitstreams for the following devices:
Ti135N576, Ti85N576
Tz100N576, Tz75N576
Reduces place and route compile times by about ~30%
Significantly improves responsiveness of the Efinity Floorplan Viewer and Console
Improves Python toolkit with efx_py Python tool that lets you create and modify projects with Python scripting
Adds Automated Option Explorer (AOE) scripting tool efx_run_aoe.py
Explore synthesis and placement compiler options
Search for combinations that achieve the highest fMAX across system clocks
Adds GUI Console customization options; limit, filter, or suppress compiler messages
Allows multiple Interface Designer project files to exist in an Efinity project directory
Adds a smart bit-generator compiler shortcut to the Interface Designer to generate a new bitstream quickly when changes to do not require re-running place-and route
Adds dark theme option to Efinity GUI
Introduces beta support for design partitions:
Using the Efinity Partition Planner, users can preserve and export/import synthesis, placement, and routing results of design instances within bounded rectangular partitions in the core fabric
Using partitions can ease integration of validated design components into a single FPGA design, and works well with team-based design and incremental compile flows