FPGA and AI

[antti]

AI is getting better and better with FPGA development work, right now I have used codex/Claude in 3 actual VHDL projects and Claude helped a lot writing TCL timing constraints.

So instead of reading PDF I usually just ask Claude when I have a problem or warning in the FPGA tools logs.

This works with general AI's, but there is one FPGA special AI:

https://chipnexus.ai/

I have tried not out chipnexus but I tried the older version of their tools (primis.ai), I was not impressed. So I can not say chipnexus is better than Codex/Claude.

[zapta]

If codex/Claude free or per-fee? Do you use it professionally or for hobby? How much does it cost you a month?

I heard stories about development teams whose productivity is not limited by the team size but by their AI budget.

EDIT: I considered in the past adding AI integration for Apio, for example a command that would invoke AI tools to generated Apio friendly test benches but couldn't find a solution that would work for free out of the box so ended up documenting prompt that people can use on their own. https://fpgawars.github.io/apio/docs/using-testbenches/#instructions-for-ai

[marshallh]

It is improving but still has some severe drawbacks with HDL as compared to software. Chiefly that it still has no understanding of the timing relationships that HDL can produce.

As a result, it only works well if you can stick to very small, tightly scoped modules similar to what already exists on Github.. It has no trouble working with those and plugging them together.

Claude 5's pattern recognition is impressive but still not enough since it does not and cannot model signal waveforms themselves. If you need complex relationships with custom logic and custom busses, it won't work. If you are just wiring up axi/wishbone devices together it can save some time.

I did evaluate Primis last year and it was just a vector search + VScode plugin, created to fill the niche of middle managers satisfying an AI mandate.

Asking Claude specific questions to save time reading docs has been hit or miss for me. I won't say it's useless, but it does and will hallucinate features and descriptions that never existed. So it's more like a last ditch hail mary before I dive back into the docs and find what they actually say.

[betocool]

I've been using Sonnet 5 at work, heck, we all are, and I use it a lot for Firmware and VHDL in a medium complexity project. It is faster that I am at typing and I think it comes up with good ideas most of the time. Still it needs supervision, and simulation of course. At least it's very good at writing complex test benches, getting tedious TCL stuff done, and all the input/output instantiation.

I was chatting about that with our team, software, mechs, elecs, etc... I'm not sure I'm faster per se, but I do get more stuff done in parallel, or so it feels like.

I'm in the middle of refactoring some PLL related code, if I had to do it myself it'd take me much longer. Or maybe I'm not as good as I thought I was... 

My 2c.

Cheers,

Alberto

[nctnico]

I've been using Sonnet 5 at work, heck, we all are, and I use it a lot for Firmware and VHDL in a medium complexity project. It is faster that I am at typing and I think it comes up with good ideas most of the time. Still it needs supervision, and simulation of course. At least it's very good at writing complex test benches, getting tedious TCL stuff done, and all the input/output instantiation.

Same here. For a speed sensitive design I got Claude to try a couple of approaches and then let Claude help validating the results from testing on actual hardware. However, Claude didn't really do well on coming up with a really good approach by itself.

[paulca]

I was working my way through tutorials again.  Starting back with UART to get back into learning HDL again.  The goal was a simple clocked loop "task" I could fire off to print debug nonesense to a UART.  log("Hello world") or whatever.

I had one issue with the signalling.  How does the UART signal it's done with this byte and is ready for another.  In my software trained mind I used what would be referred to their as a semiphore. 

FPGA synthesis said, "XXXX URrr Urrrrr".  Conflicting drivers for Signal X.

I asked claude, in the terminal, in VSCode.  It did not answer me.  Not one word.  The first thing that happened was a code diff window opened and half my uart.v was rewritten in it.  This proceeded with the top.v and the test bench.  At least 25% edits to each.

Then and only then did it tell me what it found, what it fixed and why.

This was all well and good, but I sat and stared at it and realised I had just destroyed my learning project by letting it do that.  The point is, I didn't do it.  Therefore I learnt nothing.

[Siwastaja]

I asked claude, in the terminal, in VSCode.  It did not answer me.  Not one word.  The first thing that happened was a code diff window opened and half my uart.v was rewritten in it.  This proceeded with the top.v and the test bench.  At least 25% edits to each.

Then and only then did it tell me what it found, what it fixed and why.

This was all well and good, but I sat and stared at it and realised I had just destroyed my learning project by letting it do that.  The point is, I didn't do it.  Therefore I learnt nothing.

This seems to be the default behavior of Claude Code after Fable shipped. It was also kind of shocking when it started to act like that suddenly. The results are great - it just sits quiet and figures out what you need and solves the problem very robustly. At the same time, the silence is scary. I have mixed feelings about it. When I want the problem solved, it's like watching a human expert concentrate on the problem and do things without babbling about it, then in the end summarize. Same thing. Clearly AI doesn't need as much handholding as it did a year ago. Hence, makes sense to silence the steps by default. And then again, sometimes those steps and fun and educational to follow. If you don't want to follow, you can just look the other way, that's easier than any configuration change.

But, it took some time to figure out it's not an actual behavior change of the model. It's just a UI/UX change. Turn on the summarized thinking, and lo and behold, all those steps and reasoning between tool calls comes back. So you have a choice!

[KE5FX]

True, a lot of the narration went away recently, but at least some of it can be turned back on.

I can't imagine wasting time with Sonnet when it comes to something like HDL work.  It's Fable or nothing for me these days.  If I want Sonnet-level performance, I can get that from the server in my basement.

[glenenglish]

what I find is that any MCP/AI tool is hopeless when it comes to comprehending  some AXI4 stream actions.
even if its constrained like hell. The logic engine just doesnt seem to be able to figure out how to handle all the combinations of AXI4 stream handshakes robustly.

For paths with valid rate = clock, with the odd random ready-deassert thrown in for one cycle only, the results are worse. To deal with that I find you need a combinatorial path in there. 
It's one of the limiations of simulation, where you need to observe behaviour in the system and respnd.  like jittery and bursty real world event data sources, tied with data sinks that are also discontinuous in acceptance of data. Sure fifos everywhere are useful, but that leads to latency control slop...

anyone else faced the above ?

[paulca]

Thinking about the "UART incident".  In reflection I "drop prompted" a brand new session with something like:

"We worked on a bug prior and it's fixed, but it still doesn't behave correct <insert the behaviour>.  It should behave like a proper UART IC with a TX_DATA register latched by CE... "

Or something similar.  Note how that contains a very clear goal.  Easily expanded via a search into any of a million tutorials and reddit posts on UART HDL.

So it just didn't talk about, it made it work like an UART IC and handed it back to me.  Some of it is still confusing to me, most is ok.  But on the plus side it does actually behave like a modern UART with a "latched TX" in addition to the byte being clocked out at that moment.