generating Verilog from a schemetic (ICESTUDIO code versus DIGITAL code)

[dentaku]

I've never used an FPGA and was looking for a free tool that lets you draw simple logic circuits and generate Verilog from it.
So far I've found IceStudiohttps://icestudio.io/ and a version of logisim named Digital https://github.com/hneemann/Digital.

QUESTION:
What's with all the extra code IceStudio adds?
Digital just creates a few simple lines of Verilog but IceStudio uses all kinds of random names for modules and adds lots of "wires".
Are there any other free programs that generate Verilog from schematics?

Code: [Select]

/*
 * Generated by Digital. Don't modify this file!
 * Any changes will be lost if this file is regenerated.
 */

module \XOR-Digital(logisim)  (
  input a,
  input b,
  output out
);
  assign out = (a ^ b);
endmodule
compared to this for the same basic single 2 input one output circuit

Code: [Select]

// Code generated by Icestudio 0.5.0
// Thu, 05 Dec 2019 02:58:38 GMT

`default_nettype none

module main (
 input v64ad1c,
 input v1a9680,
 output v7a285f
);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = v64ad1c;
 assign w1 = v1a9680;
 assign v7a285f = w2;
 ve9ceb2 v29cf4e (
  .v0e28cb(w0),
  .v3ca442(w1),
  .vcbab45(w2)
 );
endmodule

module ve9ceb2 (
 input v0e28cb,
 input v3ca442,
 output vcbab45
);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = v0e28cb;
 assign w1 = v3ca442;
 assign vcbab45 = w2;
 ve9ceb2_vf4938a vf4938a (
  .a(w0),
  .b(w1),
  .c(w2)
 );
endmodule

module ve9ceb2_vf4938a (
 input a,
 input b,
 output c
);
 // XOR logic gate
 
 assign c = a ^ b;
endmodule


[BrianHG]

Here is Quartus Prime:

After selecting ' Create HDL File From Current Design File '  (Selected Verilog mode... )

File : xor1.v

Code: [Select]

// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
// CREATED "Fri Dec 06 22:57:49 2019"

module xor1(
A,
B,
Q
);


input wire A;
input wire B;
output wire Q;





assign Q = A ^ B;


endmodule

Note that labeling buses in Quartus uses .. instead of :   Example:

Verilog: data_bus[7:0]
Quartus schematic:  data_bus[7..0]

Quartus automatically translates their .. to the : when they generate the verilog code.


Older versions of Quartus, like v9.1 have a quick built in wysiwyg simulator.
Quartus prime uses Modelsim.

[ebclr]

I'm interested in make some https://github.com/FPGAwars/Alhambra-II-FPGA bords, anybody interested in a group buy?

[rstofer]

Back when ISE was the Xilinx toolchain, it was possible to do schematic entry.  Now that Vivado has come along, that capability is gone.
Schematic entry might have made sense when designs (and chips) were small, about the size of CPLDs.  It just doesn't make sense for the kinds of things folks are doing today.

It is just a whole lot easier to write something like Z <= X XOR Y; than it is to draw it out and then have to instantiate it as a component.

These days, Modelsim has a Student Edition that is free.  This was not the case about 15 years ago when I started playing with this stuff.  As a result, you can code and simulate projects quite quickly.  Of course, there is the issue of writing test benches but for some minimal circuit, this shouldn't be a big deal.  In fact, the entire Latice tool chain is quite nice in an 'old school' kind of way.  Since I only use Xilinx, I guess I will stick with Vivado because it has a simulator and, better yet, an Internal Logic Analyzer that lets me debug the actual hardware.  It's a huge and slow toolchain but it works quite well.

A high end PC is recommended for Vivado.  During synthesis, the tool will use up to 8 threads and it needs every one of them.  The WebPack version is free but it doesn't use the higher thread count for place and route (where it needs it) or bitstream generation.  But it's free so I don't complain!

Modelsim will run adequately on just about anything.  It doesn't have to do any of the complex tasks like systhesis, place and route or bitstream generation so it compiles FAST.

[dentaku]

Interesting.
It's unfortunate the free version isn't available on Windows for some reason.

Here is Quartus Prime:
(Attachment Link)
After selecting ' Create HDL File From Current Design File '  (Selected Verilog mode... )

File : xor1.v

Code: [Select]

// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
// CREATED "Fri Dec 06 22:57:49 2019"

module xor1(
A,
B,
Q
);


input wire A;
input wire B;
output wire Q;





assign Q = A ^ B;


endmodule

Note that labeling buses in Quartus uses .. instead of :   Example:

Verilog: data_bus[7:0]
Quartus schematic:  data_bus[7..0]

Quartus automatically translates their .. to the : when they generate the verilog code.


Older versions of Quartus, like v9.1 have a quick built in wysiwyg simulator.
Quartus prime uses Modelsim.

[dentaku]

I figured someone would mention about schematic entry being impractical but it still interests me.
My brain just prefers working that way instead of just typing in code.
I know it's only good for very simple things but I don't want to use an FPGA for anything much more complicated than a circuit built of old logic ICs at the moment.
As I learn more about HDLs I can write more code.

Back when ISE was the Xilinx toolchain, it was possible to do schematic entry.  Now that Vivado has come along, that capability is gone.
Schematic entry might have made sense when designs (and chips) were small, about the size of CPLDs.  It just doesn't make sense for the kinds of things folks are doing today.

It is just a whole lot easier to write something like Z <= X XOR Y; than it is to draw it out and then have to instantiate it as a component.

These days, Modelsim has a Student Edition that is free.  This was not the case about 15 years ago when I started playing with this stuff.  As a result, you can code and simulate projects quite quickly.  Of course, there is the issue of writing test benches but for some minimal circuit, this shouldn't be a big deal.  In fact, the entire Latice tool chain is quite nice in an 'old school' kind of way.  Since I only use Xilinx, I guess I will stick with Vivado because it has a simulator and, better yet, an Internal Logic Analyzer that lets me debug the actual hardware.  It's a huge and slow toolchain but it works quite well.

A high end PC is recommended for Vivado.  During synthesis, the tool will use up to 8 threads and it needs every one of them.  The WebPack version is free but it doesn't use the higher thread count for place and route (where it needs it) or bitstream generation.  But it's free so I don't complain!

Modelsim will run adequately on just about anything.  It doesn't have to do any of the complex tasks like systhesis, place and route or bitstream generation so it compiles FAST.

[BrianHG]

Interesting.
It's unfortunate the free version isn't available on Windows for some reason.

Here is Quartus Prime:
(Attachment Link)
After selecting ' Create HDL File From Current Design File '  (Selected Verilog mode... )

File : xor1.v

Code: [Select]

// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
// CREATED "Fri Dec 06 22:57:49 2019"

module xor1(
A,
B,
Q
);


input wire A;
input wire B;
output wire Q;





assign Q = A ^ B;


endmodule

Note that labeling buses in Quartus uses .. instead of :   Example:

Verilog: data_bus[7:0]
Quartus schematic:  data_bus[7..0]

Quartus automatically translates their .. to the : when they generate the verilog code.


Older versions of Quartus, like v9.1 have a quick built in wysiwyg simulator.
Quartus prime uses Modelsim.

18.1 and 19.1 free versions are available for Windows.  The latest one wont download.